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? 2011 microchip technology inc. preliminary ds41569a pic16lf1904/6/7 data sheet 28/40/44-pin flash-based, 8-bit cmos microcontrollers with lcd driver and nanowatt xlp technology
ds41569a-page 2 preliminary ? 2011 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-028-8 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2011 microchip technology inc. preliminary ds41569a-page 3 pic16lf1904/6/7 high-performance risc cpu: ? c compiler optimized architecture ? only 49 instructions ? up to 14 kbytes self-write/read flash program memory addressing ? up to 256 bytes data memory addressing ? operating speed: - dc ? 20 mhz clock input @ 3.6v - dc ? 16 mhz clock input @ 1.8v - dc ? 200 ns instruction cycle ? interrupt capability with automatic context saving ? 16-level deep hardware stack with optional overflow/underflow reset ? direct, indirect and relative addressing modes: - two full 16-bit file select registers (fsrs) - fsrs can read program and data memory flexible oscillator structure: ? 16 mhz internal oscillator block: - accuracy to 3%, typical - software selectable frequency range from 16 mhz to 31.25 khz ? 31 khz low-power internal oscillator ? three external clock modes up to 20 mhz ? two-speed oscillator start-up ? low-power rtc implementation via lpt1osc special microcontroller features: ? operating voltage range: -1.8v-3.6v ? self-programmable under software control ? power-on reset (por) ? power-up timer (pwrt) ? low-power brown-out reset (lpbor) ? extended watchdog timer (wdt) ? in-circuit serial programming? (icsp?) via two pins ? in-circuit debug (icd) via two pins ? enhanced low-voltage programming (lvp) ? programmable code protection ? power-saving sleep mode extreme low-power management pic16lf1904/6/7 with nanowatt xlp: ? sleep mode: 30 na @ 1.8v, typical ? watchdog timer: 300 na @ 1.8v, typical ? timer1 oscillator: 500 na @ 1.8v, typical analog features: ? analog-to-digital converter (adc): - 10-bit resolution, up to 14 channels - conversion available during sleep - dedicated adc rc oscillator - fixed voltage reference (fvr) as channel ? integrated temperature indicator ? voltage reference module: - fixed voltage reference (fvr) with 1.024v and 2.048v output levels peripheral highlights: ? up to 36 i/o pins and 1 input-only pin: - high current 25 ma sink/source - individually programmable weak pull-ups - individually programmable interrupt-on- change (ioc) pins ? integrated lcd controller: - at least 19 segment pins and as many as 116 total segments - variable clock input - contrast control - internal voltage reference selections ? timer0: 8-bit timer/counter with 8-bit programmable prescaler ? enhanced timer1: - 16-bit timer/counter with prescaler - external gate input mode - dedicated low-power 32 khz oscillator driver ? enhanced universal synchronous asynchronous receiver transmitter (eusart): - rs-232, rs-485 and lin compatible - auto-baud detect - auto-wake-up on start 28/40/44-pin 8-bit flash microcontrollers with nanowatt xlp technology
pic16lf1904/6/7 ds41569a-page 4 preliminary ? 2011 microchip technology inc. pic16lf1904/6/7 family types figure 1: 28-pin pdip, soic, ssop package diagram for pic16lf1906 device program memory flash (words) sram (bytes) i/os 10-bit a/d (ch) timers 8/16-bit eusart lcd common pins segment pins total segments pic16lf1904 4096 256 36 14 1/1 1 4 29 116 pic16lf1906 8192 512 25 11 1/1 1 4 19 72 (1) pic16lf1907 8192 512 36 14 1/1 1 4 29 116 note 1: com3 and seg15 share a pin, so the total segments are limited to 72 for 28 pin devices. pic16lf1906 1 2 3 4 5 6 7 8 9 10 v pp /mclr /re3 seg12/an0/ra0 seg7/an1/ra1 com2/an2/ra2 seg15/com3/v ref +/an3/ra3 seg4/t0cki/ra4 seg5/an4/ra5 rb6/icspclk/icdclk/seg14 rb5/an13/com1 rb4/an11/com0 rb3/an9/seg26/vlcd3 rb2/an8/seg25/vlcd2 rb1/an10/seg24/vlcd1 rb0/an12/int/seg0 v dd v ss 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 v ss seg2/clkin/ra7 seg1/clkout/ra6 t1cki/t1oso/rc0 t1osi/rc1 seg3/rc2 seg6/rc3 rc5/seg10 rc4/t1g/seg11 rc7/rx/dt/seg8 rc6/tx/ck/seg9 rb7/icspdat/icddat/seg13 28-pin pdip, soic, ssop
? 2011 microchip technology inc. preliminary ds41569a-page 5 pic16lf1904/6/7 figure 2: 28-pin uqfn packag e diagram for pic16lf1906 28-pin uqfn 2 3 6 1 18 19 20 21 15 7 16 17 t1cki/t1oso/rc0 5 4 rb7/icspdat/icddat/seg13 rb6/icspclk/icdclk/seg14 rb5/an13/com1 rb4/an11/com0 rb0/an12/int/seg0 v dd v ss rc7/rx/dt/seg8 seg9/ck/tx/rc6 seg10/rc5 seg11/t1g/rc4 re3/mclr /v pp ra0/an0/seg12 ra1/an1/seg7 com2/an2/ra2 seg15/com3/v ref +/an3/ra3 seg4/t0cki/ra4 seg5/an4/ra5 v ss seg2/clkin/ra7 seg1/clkout/ra6 t1osi/rc1 seg3/rc2 seg6/rc3 9 10 13 8 14 12 11 27 26 23 28 22 24 25 pic16lf1906 rb3/an9/seg26/vlcd3 rb2/an8/seg25/vlcd2 rb1/an10/seg24/vlcd1
pic16lf1904/6/7 ds41569a-page 6 preliminary ? 2011 microchip technology inc. figure 3: 40-pin pdip packag e diagram for pic16lf1904/7 40-pin pdip pic16lf1904/7 2 3 4 5 6 7 8 9 10 v pp /mclr /re3 seg12/an0/ra0 seg7/an1/ra1 com2/an2/ra2 seg15/v ref +/an3/ra3 seg4/t0cki/ra4 seg5/an4/ra5 seg21/an5/re0 seg22/an6/re1 seg23/an7/re2 rb6/icspclk/icdclk/seg14 rb5/an13/com1 rb4/an11/com0 rb0/an12/int/seg0 v dd v ss rd2/seg28 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v dd v ss seg2/clkin/ra7 seg1/clkout/ra6 t1cki/t1oso/rc0 t1osi/rc1 seg3/rc2 seg6/rc3 com3/rd0 seg27/rd1 rc5/seg10 rc4/t1g/seg11 rd3/seg16 rd4/seg17 rc7/rx/dt/seg8 rc6/tx/ck/seg9 rd7/seg20 rd6/seg19 rd5/seg18 rb7/icspdat/icddat/seg13 1 rb3/an9/seg26 / vlcd3 rb2/an8/seg25/vlcd2 rb1/an10/seg24/vlcd1
? 2011 microchip technology inc. preliminary ds41569a-page 7 pic16lf1904/6/7 figure 4: 44-pin tqfp (10x10) package diagram for pic16lf1904/7 44-pin tqfp (10x10) 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 5 4 pic16lf1904/7 rc6/tx/ck/seg9 rc5/seg10 rc4/t1g/seg11 rd3/seg16 rd2/seg28 rd1/seg27 rd0/com3 rc3/seg6 rc2/seg3 rc1/t1osi rc0/t1oso/t1cki seg7/an1/ra1 seg12/an0/ra0 v pp /mclr /re3 vlcd3/seg26 / an9/rb3 seg13/icddat/icspdat/rb7 seg14/icdclk/icspclk/rb6 com1/an13/rb5 com0/an11/rb4 nc seg15/v ref +/an3/ra3 com2/an2/ra2 seg8/dt/rx/rc7 seg17/rd4 seg18/rd5 seg19/rd6 seg20/rd7 v ss v dd seg0/int/an12/rb0 vlcd1/seg24/an10/rb1 vlcd2/seg25/an8/rb2 ra6/clkout/seg1 ra7/clkin/seg2 v ss nc v dd re2/an7/seg23 re1/an6/seg22 re0/an5/seg21 ra5/an4/seg5 ra4/t0cki/seg4 nc nc
pic16lf1904/6/7 ds41569a-page 8 preliminary ? 2011 microchip technology inc. figure 5: 40-pin uqfn (5x5) p ackage diagram for pic16lf1904/7 40-pin uqfn (5x5) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 seg7/an1/ra1 seg12/an0/ra0 v pp /mclr /re3 vlcd3/seg26 / an9/rb3 seg13/icddat/icspdat/rb7 seg14/icdclk/icspclk/rb6 com1/an13/rb5 com0/an11/rb4 rc6/tx/ck/seg9 rc5/seg10 rc4/t1g/seg11 rd3/seg16 rd2/seg28 rd1/seg27 rd0/com3 rc3/seg6 rc2/seg3 rc1/t1osi rc0/t1oso/t1cki ra6/clkout/seg1 ra7/clkin/seg2 v ss v dd re2/an7/seg23 re1/an6/seg22 re0/an5/seg21 ra5/an4/seg5 ra4/t0cki/seg4 seg8/dt/rx/rc7 seg17/rd4 seg18/rd5 seg19/rd6 seg20/rd7 v ss v dd seg0/int/an12/rb0 vlcd1/seg24/an10/rb1 vlcd2/seg25/an8/rb2 pic16lf1904/7 seg15/v ref +/an3/ra3 com2/an2/ra2
? 2011 microchip technology inc. preliminary ds41569a-page 9 pic16lf1904/6/7 table 1: 28/40/44-pin allocation table (pic16lf1904/6/7) i/o 28-pin pdip/ soic/ssop (2) 28-pin uqfn (2) 40-pin pdip (3) 44-pin tqfp 40-pin uqfn a/d timers eusart lcd interrupt pull-up basic ra0 2 27 2 19 17 an0 ? ? seg12 ? ? ? ra1 3 28 3 20 18 an1 ? ? seg7 ? ? ? ra2 4 1 4 21 19 an2 ? ? com2 ? ? ? ra3 5 2 5 22 20 an3/ v ref + ? ? seg15/ com3 (2) ?? ? ra4 6 3 6 23 21 ? t0cki ? seg4 ? ? ? ra5 7 4 7 24 22 an4 ? ? seg5 ? ? ? ra6 10 7 14 31 29 ? ? ? seg1 ? ? clkout ra79 6 133028 ? ? ? seg2 ?? clkin rb0 21 18 33 8 8 an12 ? ? seg0 int/ ioc y ? rb1 22 19 34 9 9 an10 ? ? vlcd1/ seg24 ioc y ? rb2 23 20 35 10 10 an8 ? ? vlcd2/ seg25 ioc y ? rb32421361111an9 ? ? vlcd3/ seg26 ioc y ? rb4 25 22 37 14 12 an11 ? ? com0 ioc y ? rb52623381513an13? ? com1iocy ? rb6 27 24 39 16 14 ? ? ? seg14 ioc y icspclk/ icdclk rb72825401715 ? ? ? seg13iocy icspdat/ icddat rc0 11 8 15 32 30 ? t1oso/ t1cki ? ? ? ? ? rc112 9 163531 ?t1osi ? ? ?? ? rc2 13 10 17 36 32 ? ? ? seg3 ? ? ? rc31411183733 ? ? ? seg6 ?? ? rc4 15 12 23 42 38 ? t1g ? seg11 ? ? ? rc51613244339 ? ? ? seg10?? ? rc6 17 14 25 44 40 ? ? tx/ck seg9 ? ? ? rc7 18 15 26 1 1 ? ? rx/dt seg8 ? ? ? rd0 ? ? 19 38 34 ? ? ? com3 (3) ? ? ? rd1? ?203935 ? ? ? seg27?? ? rd2 ? ? 21 40 36 ? ? ? seg28 ? ? ? rd3? ?224137 ? ? ? seg16?? ? rd4 ? ? 27 2 2 ? ? ? seg17 ? ? ? rd5 ? ? 28 3 3 ? ? ? seg18 ? ? ? rd6 ? ? 29 4 4 ? ? ? seg19 ? ? ? rd7 ? ? 30 5 5 ? ? ? seg20 ? ? ? re0 ? ? 8 25 23 an5 ? ? seg21 ? ? ? re1 ? ? 9 26 24 an6 ? ? seg22 ? ? ? re2 ? ? 10 27 25 an7 ? ? seg23 ? ? ? re312611816 ? ? ? ? ?y (1) mclr /v pp v dd 20 17 11,32 7,28 7, 26 ? ? ? ? ? ? v dd vss 8,19 5,16 12,31 6,29 6, 27 ? ? ? ? ? ? v ss nc ? ? ? 12,13, 33,34 ? ? ? ? ? ? ? v dd note 1: weak pull-up always enabled when mclr is enabled, otherwise the pull-up is under user control. 2: 28-pin only pin location (pic16lf1906). location different on 40/44-pin device. 3: 40/44-pin only pin location (pic16lf1904/1907). location different on 28-pin device.
pic16lf1904/6/7 ds41569a-page 10 preliminary ? 2011 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ........................................................... 13 2.0 enhanced mid-range cpu ...................................................................................................... .................................................. 19 3.0 memory organization ......................................................................................................... ........................................................ 21 4.0 device configuration ........................................................................................................ .......................................................... 43 5.0 resets ...................................................................................................................... .................................................................. 49 6.0 oscillator module........................................................................................................... ............................................................. 57 7.0 interrupts .................................................................................................................. .................................................................. 67 8.0 power-down mode (sleep) ..................................................................................................... ................................................... 79 9.0 watchdog timer (wdt) ........................................................................................................ ..................................................... 81 10.0 flash program memory control ............................................................................................... .................................................. 85 11.0 i/o ports .................................................................................................................. ................................................................. 101 12.0 interrupt-on-change ........................................................................................................ ......................................................... 117 13.0 fixed voltage reference (fvr) .............................................................................................. ................................................. 121 14.0 temperature indicator ...................................................................................................... ........................................................ 123 15.0 analog-to-digital converter (adc) module ................................................................................... ........................................... 125 16.0 timer0 module .............................................................................................................. ........................................................... 139 17.0 timer1 module .............................................................................................................. ........................................................... 143 18.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) .................................................. ............. 155 19.0 liquid crystal display (lcd) driver module ................................................................................. ............................................ 185 20.0 in-circuit serial programming ? (icsp ? ) .............................................................................................................................. .. 219 21.0 instruction set summary .................................................................................................... ...................................................... 223 22.0 electrical specifications.................................................................................................. .......................................................... 237 23.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 255 24.0 development support........................................................................................................ ....................................................... 257 25.0 packaging information...................................................................................................... ........................................................ 261 appendix a: revision history................................................................................................... .......................................................... 277 index .......................................................................................................................... ........................................................................ 279 the microchip web site ......................................................................................................... ............................................................ 285 customer change notification service ........................................................................................... ................................................... 285 customer support ............................................................................................................... ............................................................... 285 reader response ................................................................................................................ .............................................................. 286 product identification system.................................................................................................. ........................................................... 287
? 2011 microchip technology inc. preliminary ds41569a-page 11 pic16lf1904/6/7 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literature center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de literature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
pic16lf1904/6/7 ds41569a-page 12 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 13 pic16lf1904/6/7 1.0 device overview the pic16lf1904/6/7 are described within this data sheet. they are available in 28, 40 and 44-pin pack- ages. figure 1-1 shows a block diagram of the pic16lf1904/6/7 devices. ta bl e 1 - 2 shows the pinout descriptions. reference tab l e 1 - 1 for peripherals available per device. table 1-1: device peripheral summary peripheral pic16lf1906 pic16lf1904/7 adc eusart fixed voltage reference (fvr) lcd temperature indicator timers timer0 timer1
pic16lf1904/6/7 ds41569a-page 14 preliminary ? 2011 microchip technology inc. figure 1-1: pic16lf1 904/6/7 block diagram porta timer1 timer0 portb portc portd lcd note 1: see applicable chapters for more information on peripherals. cpu program flash memory ram timing generation intrc oscillator mclr figure 2-1 clkin clkout adc 10-bit fvr te m p . indicator eusart porte
? 2011 microchip technology inc. preliminary ds41569a-page 15 pic16lf1904/6/7 table 1-2: pic16lf1904/6/7 pinout description name function input type output type description ra0/an0/seg12 ra0 ttl cmos general purpose i/o. an0 an ? a/d channel 0 input. seg12 ? an lcd analog output. ra1/an1/seg7 ra1 ttl cmos general purpose i/o. an1 an ? a/d channel 1 input. seg7 ? an lcd analog output. ra2/an2/com2 ra2 ttl cmos general purpose i/o. an2 an ? a/d channel 2 input. com2 ? an lcd analog output. ra3/an3/v ref +/com3 (2) / seg15 ra3 ttl cmos general purpose i/o. an3 an ? a/d channel 3 input. v ref + an ? a/d voltage reference input. com3 ? an lcd analog output. seg15 ? an lcd analog output. ra4/t0cki/seg4 ra4 ttl cmos general purpose i/o. t0cki st ? timer0 clock input. seg4 ? an lcd analog output. ra5/an4/seg5 ra5 ttl cmos general purpose i/o. an4 an ? a/d channel 4 input. seg5 ? an lcd analog output. ra6/clkout/seg1 ra6 ttl cmos general purpose i/o. clkout ? cmos f osc /4 output. seg1 ? an lcd analog output. ra7/clkin/seg2 ra7 ttl cmos general purpose i/o. clkin cmos ? external clock input (ec mode). seg2 ? an lcd analog output. rb0/an12/int/seg0 rb0 ttl cmos general purpose i/o. an12 an ? a/d channel 12 input. int st ? external interrupt. seg0 ? an lcd analog output. rb1 (1) /an10/seg24/vlcd1 rb1 ttl cmos general purpose i/o. an10 an ? a/d channel 10 input. seg24 ? an lcd analog output. vlcd1 an ? lcd analog input. rb2 (1) /an8/seg25/vlcd2 rb2 ttl cmos general purpose i/o. an8 an ? a/d channel 8 input. seg25 ? an lcd analog output. vlcd2 an ? lcd analog input. legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: these pins have interrupt -on-change functionality. 2: pic16lf1906/7 only.
pic16lf1904/6/7 ds41569a-page 16 preliminary ? 2011 microchip technology inc. rb3 (1) /an9/seg26/vlcd3 rb3 ttl cmos general purpose i/o. an9 an ? a/d channel 9 input. seg26 ? an lcd analog output. vlcd3 an ? lcd analog input. rb4 (1) /an11/com0 rb4 ttl cmos general purpose i/o. an11 an ? a/d channel 11 input. com0 ? an lcd analog output. rb5 (1) /an13/com1 rb5 ttl cmos general purpose i/o. an13 an ? a/d channel 13 input. com1 ? an lcd analog output. rb6 (1) /icspclk/icdclk/ seg14 rb6 ttl cmos general purpose i/o. icspclk st ? serial programming clock. icdclk st ? in-circuit debug clock. seg14 ? an lcd analog output. rb7 (1) /icspdat/icddat/ seg13 rb7 ttl cmos general purpose i/o. icspdat st ? serial programming clock. icddat st cmos in-circuit data i/o. seg13 ? an lcd analog output. rc0/t1oso/t1cki rc0 ttl cmos general purpose i/o. t1oso xtal xtal timer1 oscillator connection. t1cki st ? timer1 clock input. rc1/t1osi rc1 ttl cmos general purpose i/o. t1osi xtal xtal timer1 oscillator connection. rc2/seg3 rc2 ttl cmos general purpose i/o. seg3 ? an lcd analog output. rc3/seg6 rc3 ttl cmos general purpose i/o. seg6 ? an lcd analog output. rc4/t1g/seg11 rc4 ttl cmos general purpose i/o. t1g xtal xtal timer1 oscillator connection. seg11 ? an lcd analog output. rc5/seg10 rc5 ttl cmos general purpose i/o. seg10 ? an lcd analog output. rc6/tx/ck/seg9 rc6 ttl cmos general purpose i/o. tx ? cmos usart asynchronous transmit. ck st cmos usart synchronous clock. seg9 ? an lcd analog output. rc7/rx/dt/seg8 rc7 ttl cmos general purpose i/o. rx st ? usart asynchronous input. dt st cmos usart synchronous data. seg8 ? an lcd analog output. table 1-2: pic16lf1904/6/7 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: these pins have interrupt -on-change functionality. 2: pic16lf1906/7 only.
? 2011 microchip technology inc. preliminary ds41569a-page 17 pic16lf1904/6/7 rd0 (2) /com3 rd0 ttl cmos general purpose i/o. com3 ? an lcd analog output. rd1 (2) /seg27 rd1 ttl cmos general purpose i/o. seg27 ? an lcd analog output. rd2 (2) /seg28 rd2 ttl cmos general purpose i/o. seg28 ? an lcd analog output. rd3 (2) /seg16 rd3 ttl cmos general purpose i/o. seg16 ? an lcd analog output. rd4 (2) /seg17 rd4 ttl cmos general purpose i/o. seg17 ? an lcd analog output. rd5 (2) /seg18 rd5 ttl cmos general purpose i/o. seg18 ? an lcd analog output. rd6 (2) /seg19 rd6 ttl cmos general purpose i/o. seg19 ? an lcd analog output. rd7 (2) /seg20 rd7 ttl cmos general purpose i/o. seg20 ? an lcd analog output. re0 (2) /an5/seg21 re0 ttl cmos general purpose i/o. an5 an ? a/d channel 5 input. seg21 ? an lcd analog output. re1 (2) /an6/seg22 re1 ttl cmos general purpose i/o. an6 an ? a/d channel 6 input. seg22 ? an lcd analog output. re2 (2) /an7/seg23 re2 ttl cmos general purpose i/o. an7 an ? a/d channel 7 input. seg23 ? an lcd analog output. re3/mclr /v pp re3 ttl cmos general purpose i/o. mclr st ? master clear with internal pull-up. v pp hv ? programming voltage. v dd v dd power ? positive supply. v ss v ss power ? ground reference. table 1-2: pic16lf1904/6/7 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: these pins have interrupt -on-change functionality. 2: pic16lf1906/7 only.
pic16lf1904/6/7 ds41569a-page 18 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 19 pic16lf1904/6/7 2.0 enhanced mid-range cpu this family of devices contain an enhanced mid-range 8-bit cpu core. the cpu has 49 instructions. interrupt capability includes automatic context saving. the hardware stack is 16 levels deep and has overflow and underflow reset capability. direct, indirect, and relative addressing modes are available. two file select registers (fsrs) provide the ability to read program and data memory. ? automatic interrupt context saving ? 16-level stack with overflow and underflow ? file select registers ? instruction set 2.1 automatic interrupt context saving during interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. this saves stack space and user code. see section 7.5 ?automatic context saving? , for more information. 2.2 16-level stack with overflow and underflow these devices have an external stack memory 15 bits wide and 16 words deep. a stack overflow or under- flow will set the appropriate bit (stkovf or stkunf) in the pcon register, and if enabled, will cause a soft- ware reset. see section 3.4 ?stack? for more details. 2.3 file select registers there are two 16-bit file select registers (fsr). fsrs can access all file registers and program memory, which allows one data pointer for all memory. when an fsr points to program memory, there is one additional instruction cycle in instructions using indf to allow the data to be fetched. general purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. there are also new instructions to support the fsrs. see section 3.5 ?indirect addressing? for more details. 2.4 instruction set there are 49 instructions for the enhanced mid-range cpu to support the features of the cpu. see section 21.0 ?instruction set summary? for more details.
pic16lf1904/6/7 ds41569a-page 20 preliminary ? 2011 microchip technology inc. figure 2-1: core block diagram data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 12 addr mux fsr reg status reg mux alu power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation clkin clkout v dd 8 8 brown-out reset 12 3 v ss internal oscillator block configuration data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 addr mux fsr reg status reg mux alu w reg instruction decode & control timing generation v dd 8 8 3 v ss internal oscillator block configuration 15 data bus 8 14 program bus instruction reg program counter 16-level stack (15-bit) direct addr 7 ram addr addr mux indirect addr fsr0 reg status reg mux alu instruction decode and control timing generation v dd 8 8 3 v ss internal oscillator block configuration flash program memory ram fsr reg fsr reg fsr1 reg 15 15 mux 15 program memory read (pmr) 12 fsr reg fsr reg bsr reg 5
? 2011 microchip technology inc. preliminary ds41569a-page 21 pic16lf1904/6/7 3.0 memory organization these devices contain the following types of memory: ? program memory - configuration words - device id -user id - flash program memory ? data memory - core registers - special function registers - general purpose ram - common ram the following features are associated with access and control of program memory and data memory: ? pcl and pclath ?stack ? indirect addressing 3.1 program memory organization the enhanced mid-range core has a 15-bit program counter capable of addr essing 32k x 14 program memory space. table 3-1 shows the memory sizes implemented for the pic16lf1904/6/7 family. accessing a location above these boundaries will cause a wrap-around within the implemented memory space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figures 3-1 , and 3-2 ). table 3-1: device sizes and addresses device program memory space (words) last program memory address pic16lf1904 4,096 0fffh pic16lf1906/7 8,192 1fffh
pic16lf1904/6/7 ds41569a-page 22 preliminary ? 2011 microchip technology inc. figure 3-1: program memory map and stack for pic16lf1904 figure 3-2: program memory map and stack for pic16lf1906/7 pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector call , callw return , retlw stack level 1 0005h on-chip program memory page 0 07ffh rollover to page 0 0800h 0fffh 1000h 7fffh page 1 rollover to page 1 interrupt, retfie pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector stack level 1 0005h on-chip program memory page 0 07ffh rollover to page 0 0800h 0fffh 1000h 7fffh page 1 rollover to page 3 page 2 page 3 17ffh 1800h 1fffh 2000h call , callw return , retlw interrupt, retfie
? 2011 microchip technology inc. preliminary ds41569a-page 23 pic16lf1904/6/7 3.1.1 reading program memory as data there are two methods of accessing constants in pro- gram memory. the first method is to use tables of retlw instructions. the second method is to set an fsr to point to the program memory. 3.1.1.1 retlw instruction the retlw instruction can be used to provide access to tables of constants. the recommended way to create such a table is shown in example 3-1 . example 3-1: retlw instruction the brw instruction makes this type of table very sim- ple to implement. if your code must remain portable with previous generations of microcontrollers, then the brw instruction is not available so the older table read method must be used. 3.1.1.2 indirect read with fsr the program memory can be accessed as data by set- ting bit 7 of the fsrxh register and reading the match- ing indfx register. the moviw instruction will place the lower 8 bits of the addressed word in the w register. writes to the program memory cannot be performed via the indf registers. instructions that access the pro- gram memory via the fsr require one extra instruction cycle to complete. example 3-2 demonstrates access- ing the program memory via an fsr. the high directive will set bit<7> if a label points to a location in program memory. example 3-2: accessing program memory via fsr constants brw ;add index in w to ;program counter to ;select data retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw data_index call constants ;? the constant is in w constants retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw low constants movwf fsr1l movlw high constants movwf fsr1h moviw 0[indf1] ;the program memory is in w
pic16lf1904/6/7 ds41569a-page 24 preliminary ? 2011 microchip technology inc. 3.2 data memory organization the data memory is partitioned in 32 memory banks with 128 bytes in a bank. each bank consists of ( figure 3-3 ): ? 12 core registers ? 20 special function registers (sfr) ? up to 80 bytes of general purpose ram (gpr) ? 16 bytes of common ram the active bank is selected by writing the bank number into the bank select register (bsr). unimplemented memory will read as ? 0 ?. all data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two file select registers (fsr). see section 3.5 ?indirect addressing? for more information. data memory uses a 12-bit address. the upper 7 bits of the address define the bank address and the lower 5 bits select the registers/ram in that bank. 3.2.1 core registers the core registers contain the registers that directly affect the basic operation. the core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0bh/x8bh). these registers are listed below in ta b l e 3 - 2 . for detailed information, see tab l e 3 - 4 . table 3-2: core registers addresses bankx x00h or x80h indf0 x01h or x81h indf1 x02h or x82h pcl x03h or x83h status x04h or x84h fsr0l x05h or x85h fsr0h x06h or x86h fsr1l x07h or x87h fsr1h x08h or x88h bsr x09h or x89h wreg x0ah or x8ah pclath x0bh or x8bh intcon
? 2011 microchip technology inc. preliminary ds41569a-page 25 pic16lf1904/6/7 3.2.1.1 status register the status register, shown in register 3-1 , contains: ? the arithmetic status of the alu ? the reset status the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as ? 000u u1uu ? (where u = unchanged). it is recommended, therefore, that only bcf , bsf , swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits (refer to section 21.0 ?instruction set summary? ). note: the c and dc bits operate as borrow and digit borrow out bits, respectively, in subtraction. register 3-1: status: status register u-0 u-0 u-0 r-1/q r-1/q r/w-0/u r/w-0/u r/w-0/u ? ? ? to pd zdc (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as ? 0 ? bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (1) ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
pic16lf1904/6/7 ds41569a-page 26 preliminary ? 2011 microchip technology inc. 3.2.2 special function register the special function registers are registers used by the application to control the desired operation of peripheral functions in the device. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). the registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 general purpose ram there are up to 80 bytes of gpr in each data memory bank. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). 3.2.3.1 linear access to gpr the general purpose ram can be accessed in a non-banked method via the fsrs. this can simplify access to large memory structures. see section 3.5.2 ?linear data memory? for more information. 3.2.4 common ram there are 16 bytes of common ram accessible from all banks. figure 3-3: banked memory partitioning 3.2.5 device memory maps the memory maps for pic16lf1904/6/7 are as shown in table 3-3 . 0bh 0ch 1fh 20h 6fh 70h 7fh 00h common ram (16 bytes) general purpose ram (80 bytes maximum) core registers (12 bytes) special function registers (20 bytes maximum) memory region 7-bit bank offset
? 2011 microchip technology inc. preliminary ds41569a-page 27 pic16lf1904/6/7 table 3-3: pic16lf1904/6/7 memory map legend: = unimplemented data memory locations, read as ? 0 ?. note 1: pic16lf1904/7 only. bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 000h core registers ( ta b l e 3 - 2 ) 080h core registers ( ta b l e 3 - 2 ) 100h core registers ( table 3-2 ) 180h core registers ( table 3-2 ) 200h core registers ( table 3-2 ) 280h core registers ( table 3-2 ) 300h core registers ( table 3-2 ) 380h core registers ( table 3-2 ) 00bh 08bh 10bh 18bh 20bh 28bh 30bh 38bh 00ch porta 08ch trisa 10ch lata 18ch ansela 20ch ? 28ch ? 30ch ? 38ch ? 00dh portb 08dh trisb 10dh latb 18dh anselb 20dh wpub 28dh ? 30dh ? 38dh ? 00eh portc 08eh trisc 10eh latc 18eh ?20eh ?28eh ?30eh ?38eh ? 00fh portd (1) 08fh trisd (1) 10fh latd (1) 18fh ?20fh ?28fh ?30fh ?38fh ? 010h porte 090h trise (1) 110h late (1) 190h ? 210h wpue 290h ? 310h ? 390h ? 011h pir1 091h pie1 111h ? 191h pmadrl 211h ?291h ? 311h ? 391h ? 012h pir2 092h pie2 112h ? 192h pmadrh 212h ?292h ? 312h ? 392h ? 013h ?093h ?113h ? 193h pmdatl 213h ?293h ? 313h ? 393h ? 014h ?094h ?114h ? 194h pmdath 214h ?294h ? 314h ? 394h iocbp 015h tmr0 095h option_reg 115h ? 195h pmcon1 215h ?295h ? 315h ? 395h iocbn 016h tmr1l 096h pcon 116h borcon 196h pmcon2 216h ?296h ? 316h ? 396h iocbf 017h tmr1h 097h wdtcon 117h fvrcon 197h ?217h ?297h ? 317h ? 397h ? 018h t1con 098h ?118h ?198h ?218h ?298h ? 318h ? 398h ? 019h t1gcon 099h osccon 119h ? 199h rcreg 219h ?299h ? 319h ? 399h ? 01ah ? 09ah oscstat 11ah ? 19ah txreg 21ah ?29ah ?31ah ?39ah ? 01bh ? 09bhadresl11bh ? 19bh spbrg 21bh ?29bh ?31bh ?39bh ? 01ch ? 09ch adresh 11ch ? 19ch spbrgh 21ch ? 29ch ? 31ch ? 39ch ? 01dh ? 09dh adcon0 11dh ? 19dh rcsta 21dh ? 29dh ? 31dh ? 39dh ? 01eh ? 09eh adcon1 11eh ? 19eh txsta 21eh ?29eh ?31eh ?39eh ? 01fh ?09fh ?11fh ? 19fh baudcon 21fh ?29fh ?31fh ?39fh ? 020h general purpose register 96 bytes 0a0h general purpose register 80 bytes (1) 120h general purpose register 80 bytes (1) 1a0h unimplemented read as ? 0 ? 220h unimplemented read as ? 0 ? 2a0h unimplemented read as ? 0 ? 320h general purpose register 32 bytes (1) 3a0h unimplemented read as ? 0 ? 13fh 140h unimplemented read as ? 0 ? 06fh 0efh 16fh 1efh 26fh 2efh 36fh 3efh 070h 0f0h accesses 70h ? 7fh 170h accesses 70h ? 7fh 1f0h accesses 70h ? 7fh 270h accesses 70h ? 7fh 2f0h accesses 70h ? 7fh 370h accesses 70h ? 7fh 3f0h accesses 70h ? 7fh 07fh 0ffh 17fh 1ffh 27fh 2ffh 37fh 3ffh
pic16lf1904/6/7 ds41569a-page 28 preliminary ? 2011 microchip technology inc. table 3-3: pic16lf1904/6/7 memory map (continued) bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 400h 40bh core registers ( ta b l e 3 - 2 ) 480h 48bh core registers ( ta b l e 3 - 2 ) 500h 50bh core registers ( ta b l e 3 - 2 ) 580h 58bh core registers ( ta b l e 3 - 2 ) 600h 60bh core registers ( ta b l e 3 - 2 ) 680h 68bh core registers ( ta b l e 3 - 2 ) 700h 70bh core registers ( ta b l e 3 - 2 ) 40ch unimplemented read as ? 0 ? 48ch unimplemented read as ? 0 ? 50ch unimplemented read as ? 0 ? 58ch unimplemented read as ? 0 ? 60ch unimplemented read as ? 0 ? 68ch unimplemented read as ? 0 ? 70ch unimplemented read as ? 0 ? 46fh 4efh 56fh 5efh 66fh 6efh 76fh 470h common ram (accesses 70h ? 7fh) 4f0h common ram (accesses 70h ? 7fh) 570h common ram (accesses 70h ? 7fh) 5f0h common ram (accesses 70h ? 7fh) 670h common ram (accesses 70h ? 7fh) 6f0h common ram (accesses 70h ? 7fh) 770h common ram (accesses 70h ? 7fh) 47fh 4ffh 57fh 5ffh 67fh 6ffh 77fh bank 16 bank 17 bank 18 bank 19 bank 20 bank 21 bank 22 bank 23 800h 80bh core registers ( ta b l e 3 - 2 ) 880h 88bh core registers ( ta b l e 3 - 2 ) 900h 90bh core registers ( ta b l e 3 - 2 ) 980h 98bh core registers ( ta b l e 3 - 2 ) a00h a0bh core registers ( ta b l e 3 - 2 ) a80h a8bh core registers ( ta b l e 3 - 2 ) b00h b0bh core registers ( ta b l e 3 - 2 ) b80h b8bh core registers ( ta b l e 3 - 2 ) 80ch unimplemented read as ? 0 ? 88ch unimplemented read as ? 0 ? 90ch unimplemented read as ? 0 ? 98ch unimplemented read as ? 0 ? a0ch unimplemented read as ? 0 ? a8ch unimplemented read as ? 0 ? b0ch unimplemented read as ? 0 ? b8ch unimplemented read as ? 0 ? 86fh 8efh 96fh 9efh a6fh aefh b6fh befh 870h common ram (accesses 70h ? 7fh) 8f0h common ram (accesses 70h ? 7fh) 970h common ram (accesses 70h ? 7fh) 9f0h common ram (accesses 70h ? 7fh) a70h common ram (accesses 70h ? 7fh) af0h common ram (accesses 70h ? 7fh) b70h common ram (accesses 70h ? 7fh) bf0h common ram (accesses 70h ? 7fh) 87fh 8ffh 97fh 9ffh a7fh affh b7fh bffh legend: = unimplemented data memory locations, read as ? 0 ? bank 24 bank 25 bank 26 bank 27 bank 28 bank 29 bank 30 c00h c0bh core registers ( ta b l e 3 - 2 ) c80h c8bh core registers ( ta b l e 3 - 2 ) d00h d0bh core registers ( ta b l e 3 - 2 ) d80h d8bh core registers ( ta b l e 3 - 2 ) e00h e0bh core registers ( ta b l e 3 - 2 ) e80h e8bh core registers ( ta b l e 3 - 2 ) f00h f0bh core registers ( ta b l e 3 - 2 ) c0ch c6fh unimplemented read as ? 0 ? c8ch cefh unimplemented read as ? 0 ? d0ch d6fh unimplemented read as ? 0 ? d8ch defh unimplemented read as ? 0 ? e0ch e6fh unimplemented read as ? 0 ? e8ch eefh unimplemented read as ? 0 ? f0ch f6fh unimplemented read as ? 0 ? c70h common ram (accesses 70h ? 7fh) cf0h common ram (accesses 70h ? 7fh) d70h common ram (accesses 70h ? 7fh) df0h common ram (accesses 70h ? 7fh) e70h common ram (accesses 70h ? 7fh) ef0h common ram (accesses 70h ? 7fh) f70h common ram (accesses 70h ? 7fh) c7fh cffh d7fh dffh e7fh effh f7fh
? 2011 microchip technology inc. preliminary ds41569a-page 29 pic16lf1904/6/7 table 3-3: pic16lf1904/6/7 memory map (continued) legend: = unimplemented data memory locations, read as ? 0 ?. note 1: pic16lf1904/7 only. bank 15 780h 78bh core registers ( ta b l e 3 - 2 ) 78ch 790h unimplemented read as ? 0 ? 791h lcdcon 792h lcdps 793h lcdref 794h lcdcst 795h lcdrl 796h ? 797h ? 798h lcdse0 799h lcdse1 79ah lcdse2 79bh lcdse3 79ch 79fh unimplemented read as ? 0 ? 7a0h lcddata0 7a1h lcddata1 7a2h lcddata2 (1) 7a3h lcddata3 7a4h lcddata4 7a5h lcddata5 (1) 7a6h lcddata6 7a7h lcddata7 7a8h lcddata8 (1) 7a9h lcddata9 7aah lcddata10 7abh lcddata11 (1) 7ach lcddata12 7adh ? 7aeh ? 7afh lcddata15 7b0h ? 7b1h ? 7b2h lcddata18 7b3h ? 7b4h ? 7b5h lcddata21 7b6h ? 7b7h ? 7b8h 7efh unimplemented read as ? 0 ? bank 31 f80h f8bh core registers ( ta b l e 3 - 2 ) f8ch fe3h unimplemented read as ? 0 ? fe4h status_shad fe5h wreg_shad fe6h bsr_shad fe7h pclath_shad fe8h fsr0l_shad fe9h fsr0h_shad feah fsr1l_shad febh fsr1h_shad fech ? fedh stkptr feeh tosl fefh tosh ff0h common ram (accesses 70h ? 7fh) fffh
pic16lf1904/6/7 ds41569a-page 30 preliminary ? 2011 microchip technology inc. 3.2.6 core function registers summary the core function registers listed in ta bl e 3 - 4 can be addressed from any bank. table 3-4: core funct ion registers summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0-31 x00h or x80h indf0 addressing this location uses contents of fsr0h/fsr0l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or x81h indf1 addressing this location uses contents of fsr1h/fsr1l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or x82h pcl program counter (pc) least significant byte 0000 0000 0000 0000 x03h or x83h status ? ? ?to pd zdcc ---1 1000 ---q quuu x04h or x84h fsr0l indirect data memory address 0 low pointer 0000 0000 uuuu uuuu x05h or x85h fsr0h indirect data memory address 0 high pointer 0000 0000 0000 0000 x06h or x86h fsr1l indirect data memory address 1 low pointer 0000 0000 uuuu uuuu x07h or x87h fsr1h indirect data memory address 1 high pointer 0000 0000 0000 0000 x08h or x88h bsr ? ? ? bsr4 bsr3 bsr2 bsr1 bsr0 ---0 0000 ---0 0000 x09h or x89h wreg working register 0000 0000 uuuu uuuu x0ah or x8ah pclath ? write buffer for the upper 7 bits of the program counter -000 0000 -000 0000 x0bh or x8bh intcon gie peie tmr0ie inte iocie tmr0if intf iocif 0000 0000 0000 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?.
? 2011 microchip technology inc. preliminary ds41569a-page 31 pic16lf1904/6/7 table 3-5: special function register summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0 00ch porta porta data latch when written: porta pins when read xxxx xxxx uuuu uuuu 00dh portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 00eh portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 00fh portd (3) portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 010h porte ? ? ? ?re3re2 (2) re1 (2) re0 (2) ---- xxxx ---- uuuu 011h pir1 tmr1gif adif rcif txif ? ? ?tmr1if 0000 ---0 0000 ---0 012h pir2 ? ? ? ? ? lcdif ? ? ---0 -0-- ---0 -0-- 013h ? unimplemented ? ? 014h ? unimplemented ? ? 015h tmr0 timer0 module register xxxx xxxx uuuu uuuu 016h tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 017h tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 018h t1con tmr1cs1 tmr1cs0 t1ckps1 t1ckps0 t1oscen t1sync ?tmr1on 0000 00-0 uuuu uu-u 019h t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss1 t1gss0 0000 0x00 uuuu uxuu 01ah to 01fh ? unimplemented ? ? bank 1 08ch trisa porta data direction register 1111 1111 1111 1111 08dh trisb portb data direction register 1111 1111 1111 1111 08eh trisc portc data direction register 1111 1111 1111 1111 08fh trisd (3) portd data direction register 1111 1111 1111 1111 090h trise ? ? ? ? ? (2) trise2 (3) trise1 (3) trise0 (3) ---- 1111 ---- 1111 091h pie1 tmr1gie adie rcie txie ? ? ? tmr1ie 0000 ---0 0000 ---0 092h pie2 ? ? ? ? ? lcdie ? ? ---- -0-- ---- -0-- 093h ? unimplemented ? ? 094h ? unimplemented ? ? 095h option_reg wpuen intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 096h pcon stkovf stkunf ?r wdt rmclr ri por bor 00-1 11qq qq-q qquu 097h wdtcon ? ? wdtps4 wdtps3 wdtps2 wdtps1 wdtps0 swdten --01 0110 --01 0110 098h ? unimplemented ? ? 099h osccon ? ircf3 ircf2 ircf1 ircf0 ? scs1 scs0 -011 1-00 -011 1-00 09ah oscstat t1oscr ?ostshfiofr ? ? lfiofr hfiofs 0-q0 --00 q-qq --0q 09bh adresl a/d result register low xxxx xxxx uuuu uuuu 09ch adresh a/d result register high xxxx xxxx uuuu uuuu 09dh adcon0 ? chs4 chs3 chs2 chs1 chs0 go/done adon -000 0000 -000 0000 09eh adcon1 adfm adcs2 adcs1 adcs0 ? ? adpref1 adpref0 0000 ---- 0000 ---- 09fh ? unimplemented ? ? legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: these registers can be addressed from any bank. 2: unimplemented, read as ? 1 ?. 3: pic16lf1904/7 only.
pic16lf1904/6/7 ds41569a-page 32 preliminary ? 2011 microchip technology inc. bank 2 10ch lata porta data latch xxxx xxxx uuuu uuuu 10dh latb portb data latch xxxx xxxx uuuu uuuu 10eh latc portc data latch xxxx xxxx uuuu uuuu 10eh latd (3) portd data latch xxxx xxxx uuuu uuuu 10eh late (3) ? ? ? ? ? late2 late1 late0 ---- -xxx ---- -uuu 111h to 115h ? unimplemented ? ? 116h borcon sboren borfs ? ? ? ? ? borrdy 10-- ---q uu-- ---u 117h fvrcon fvren fvrrdy tsen tsrng ? ? adfvr1 adfvr0 0q00 --00 0q00 --00 118h to 11fh ? unimplemented ? ? bank 3 18ch ansela ? ? ansa5 ? ansa3 ansa2 ansa1 ansa0 --1- 1111 --11 1111 18dh anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 --11 1111 --11 1111 18eh ? unimplemented ? ? 18fh ? unimplemented ? ? 190h ansele (3) ? ? ? ? ? anse2 anse1 anse0 ---- -111 ---- -111 191h pmadrl program memory address register low byte 0000 0000 0000 0000 192h pmadrh ? program memory address register high byte 1000 0000 1000 0000 193h pmdatl program memory read data register low byte xxxx xxxx uuuu uuuu 194h pmdath ? ? program memory read data register high byte --xx xxxx --uu uuuu 195h pmcon1 ? (2) cfgs lwlo free wrerr wren wr rd 1000 x000 1000 q000 196h pmcon2 program memory control register 2 0000 0000 0000 0000 197h ? unimplemented ? ? 198h ? unimplemented ? ? 199h rcreg usart receive data register 0000 0000 0000 0000 19ah txreg usart transmit data register 0000 0000 0000 0000 19bh spbrg brg<7:0> 0000 0000 0000 0000 19ch spbrgh brg<15:8> 0000 0000 0000 0000 19dh rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19eh txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 19fh baud1con abdovf rcidl ? sckp brg16 ? wue abden 01-0 0-00 01-0 0-00 bank 4 20ch ? unimplemented ? ? 20dh wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 1111 1111 1111 1111 20eh ? unimplemented ? ? 20fh ? unimplemented ? ? 210h wpue ? ? ? ? wpue3 ? ? ? ---- 1--- ---- 1--- 211h to 21fh ? unimplemented ? ? bank 5 28ch ? 29fh ? unimplemented ? ? bank 6 30ch ? 31fh ? unimplemented ? ? table 3-5: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: these registers can be addressed from any bank. 2: unimplemented, read as ? 1 ?. 3: pic16lf1904/7 only.
? 2011 microchip technology inc. preliminary ds41569a-page 33 pic16lf1904/6/7 bank 7 38ch ? 393h ? unimplemented ? ? 394h iocbp iocbp7 iocbp6 iocbp5 iocbp4 iocbp3 iocbp2 iocbp1 iocbp0 0000 0000 0000 0000 395h iocbn iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 0000 0000 0000 0000 396h iocbf iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 0000 0000 0000 0000 397h ? 39fh ? unimplemented ? ? bank 8-14 x0ch or x8ch to x1fh or x9fh ? unimplemented ? ? bank 15 78ch ? 790h ? unimplemented ? ? 791h lcdcon lcden slpen werr ? cs1 cs0 lmux1 lmux0 000- 0011 000- 0011 792h lcdps wft biasmd lcda wa lp3 lp2 lp1 lp0 0000 0000 0000 0000 793h lcdref lcdire ? lcdiri ? vlcd3pe vlcd2pe vlcd1pe ? 0-0- 000- 0-0- 000- 794h lcdcst ? ? ? ? ? lcdcst2 lcdcst1 lcdcst0 ---- -000 ---- -000 795h lcdrl lrlap1 lrlap0 lrlbp1 lrlbp0 ? lrlat2 lrlat1 lrlat0 0000 -000 0000 -000 796h ? unimplemented ? ? 797h ? unimplemented ? ? 798h lcdse0 se7 se6 se5 se4 se3 se2 se1 se0 0000 0000 uuuu uuuu 799h lcdse1 se15 se14 se13 se12 se11 se10 se9 se8 0000 0000 uuuu uuuu 79ah lcdse2 se23 se22 se21 se20 se19 se18 se17 se16 0000 0000 uuuu uuuu 79bh lcdse3 ? ? ? se28 se27 se26 se25 se24 ---0 0000 ---u uuuu 79dh ? 79fh ? unimplemented ? ? 7a0h lcddata0 seg7 com0 seg6 com0 seg5 com0 seg4 com0 seg3 com0 seg2 com0 seg1 com0 seg0 com0 xxxx xxxx uuuu uuuu 7a1h lcddata1 seg15 com0 seg14 com0 seg13 com0 seg12 com0 seg11 com0 seg10 com0 seg9 com0 seg8 com0 xxxx xxxx uuuu uuuu 7a2h lcddata2 seg23 com0 seg22 com0 seg21 com0 seg20 com0 seg19 com0 seg18 com0 seg17 com0 seg16 com0 xxxx xxxx uuuu uuuu 7a3h lcddata3 seg7 com1 seg6 com1 seg5 com1 seg4 com1 seg3 com1 seg2 com1 seg1 com1 seg0 com1 xxxx xxxx uuuu uuuu 7a4h lcddata4 seg15 com1 seg14 com1 seg13 com1 seg12 com1 seg11 com1 seg10 com1 seg9 com1 seg8 com1 xxxx xxxx uuuu uuuu 7a5h lcddata5 seg23 com1 seg22 com1 seg21 com1 seg20 com1 seg19 com1 seg18 com1 seg17 com1 seg16 com1 xxxx xxxx uuuu uuuu 7a6h lcddata6 seg7 com2 seg6 com2 seg5 com2 seg4 com2 seg3 com2 seg2 com2 seg1 com2 seg0 com2 xxxx xxxx uuuu uuuu 7a7h lcddata7 seg15 com2 seg14 com2 seg13 com2 seg12 com2 seg11 com2 seg10 com2 seg9 com2 seg8 com2 xxxx xxxx uuuu uuuu 7a8h lcddata8 seg23 com2 seg22 com2 seg21 com2 seg20 com2 seg19 com2 seg18 com2 seg17 com2 seg16 com2 xxxx xxxx uuuu uuuu table 3-5: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: these registers can be addressed from any bank. 2: unimplemented, read as ? 1 ?. 3: pic16lf1904/7 only.
pic16lf1904/6/7 ds41569a-page 34 preliminary ? 2011 microchip technology inc. bank 15 (continued) 7a9h lcddata9 seg7 com3 seg6 com3 seg5 com3 seg4 com3 seg3 com3 seg2 com3 seg1 com3 seg0 com3 xxxx xxxx uuuu uuuu 7aah lcddata10 seg15 com3 seg14 com3 seg13 com3 seg12 com3 seg11 com3 seg10 com3 seg9 com3 seg8 com3 xxxx xxxx uuuu uuuu 7abh lcddata11 seg23 com3 seg22 com3 seg20 com3 seg19 com3 seg18 com3 seg17 com3 seg16 com3 seg15 com3 xxxx xxxx uuuu uuuu 7ach lcddata12 ? ? ? seg28 com0 seg27 com0 seg26 com0 seg25 com0 seg24 com0 ---x xxxx ---u uuuu 7adh ? unimplemented ? ? 7aeh ? unimplemented ? ? 7afh lcddata15 ? ? ? seg28 com1 seg27 com1 seg26 com1 seg25 com1 seg24 com1 ---x xxxx ---u uuuu 7b0h ? unimplemented ? ? 7b1h ? unimplemented ? ? 7b2h lcddata18 ? ? ? seg28 com2 seg27 com2 seg26 com2 seg25 com2 seg24 com2 ---x xxxx ---u uuuu 7b3h ? unimplemented ? ? 7b4h ? unimplemented ? ? 7b5h lcddata21 ? ? ? seg28 com3 seg27 com3 seg26 com3 seg25 com3 seg24 com3 ---x xxxx ---u uuuu 7b6h ? 7efh ? unimplemented ? ? bank 16-30 x0ch or x8ch to x1fh or x9fh ? unimplemented ? ? bank 31 f8ch ? fe3h ? unimplemented ? ? fe4h status_shad ? ? ? ? ? z_shad dc_shad c_shad ---- -xxx ---- -uuu fe5h wreg_shad working register normal (non-icd) shadow xxxx xxxx uuuu uuuu fe6h bsr_shad ? ? ? bank select register normal (non-icd) shadow ---x xxxx ---u uuuu fe7h pclath_shad ? program counter latch high register normal (non-icd) shadow -xxx xxxx uuuu uuuu fe8h fsr0l_shad indirect data memory address 0 low pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu fe9h fsr0h_shad indirect data memory address 0 high pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu feah fsr1l_shad indirect data memory address 1 low pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu febh fsr1h_shad indirect data memory address 1 high pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu fech ? unimplemented ? ? fedh stkptr ? ? ? current stack pointer ---1 1111 ---1 1111 feeh tosl top of stack low byte xxxx xxxx uuuu uuuu fefh tosh ? top of stack high byte -xxx xxxx -uuu uuuu table 3-5: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: these registers can be addressed from any bank. 2: unimplemented, read as ? 1 ?. 3: pic16lf1904/7 only.
? 2011 microchip technology inc. preliminary ds41569a-page 35 pic16lf1904/6/7 3.3 pcl and pclath the program counter (pc) is 15 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<14:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 3-4 shows the five situations for the loading of the pc. figure 3-4: loading of pc in different situations 3.3.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program coun- ter pc<14:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the pclath register. when the lower 8 bits are written to the pcl register, all 15 bits of the program counter will change to the values con- tained in the pclath register and those being written to the pcl register. 3.3.2 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when performing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to application note an556, ?implementing a table read? (ds00556). 3.3.3 computed function calls a computed function call allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. when performing a table read using a computed function call , care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). if using the call instruction, the pch<2:0> and pcl registers are loaded with the operand of the call instruction. pch<6:3> is loaded with pclath<6:3>. the callw instruction enables computed calls by com- bining pclath and w to form the destination address. a computed callw is accomplished by loading the w register with the desired address and executing callw . the pcl register is loaded with the value of w and pch is loaded with pclath. 3.3.4 branching the branching instructions add an offset to the pc. this allows relocatable code and code that crosses page boundaries. there are two forms of branching, brw and bra . the pc will have incremented to fetch the next instruction in both cases. when using either branching instruction, a pcl memory boundary may be crossed. if using brw , load the w register with the desired unsigned address and execute brw . the entire pc will be loaded with the address pc + 1 + w. if using bra , the entire pc will be loaded with pc + 1 +, the signed value of the operand of the bra instruction. pcl pch 0 14 pc pcl pch 0 14 pc alu result 8 7 6 pclath 0 instruction with pcl as destination goto, call opcode <10:0> 11 4 6 pclath 0 pcl pch 0 14 pc w 8 7 6 pclath 0 callw pcl pch 0 14 pc pc + w <8:0> 15 brw pcl pch 0 14 pc pc + opcode <8:0> 15 bra
pic16lf1904/6/7 ds41569a-page 36 preliminary ? 2011 microchip technology inc. 3.4 stack all devices have a 16-level x 15-bit wide hardware stack (refer to figure 3-5 ). the stack space is not part of either program or data space. the pc is pushed onto the stack when call or callw instructions are executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer if the stvren bit is programmed to ? 0 ? (configuration word 2). this means that after the stack has been pushed sixteen times, the seventeenth push overwrites the value that was stored from the first push. the eighteenth push overwrites the second push (and so on). the stkovf and stkunf flag bits will be set on an over- flow/underflow, regardless of whether the reset is enabled. 3.4.1 accessing the stack the stack is available through the tosh, tosl and stkptr registers. stkptr is the current value of the stack pointer. tosh:tosl register pair points to the top of the stack. both registers are read/writable. tos is split into tosh and tosl due to the 15-bit size of the pc. to access the stack, adjust the value of stkptr, which will position tosh:tosl, then read/write to tosh:tosl. stkptr is 5 bits to allow detection of overflow and underflow. during normal program operation, call , callw and interrupts will increment stkptr while retlw , return , and retfie will decrement stkptr. at any time stkptr can be inspected to see how much stack is left. the stkptr always points at the currently used place on the stack. therefore, a call or callw will increment the stkptr and then write the pc, and a return will unload the pc and then decrement the stkptr. reference figure 3-5 through figure 3-8 for examples of accessing the stack. figure 3-5: accessing the stack example 1 note: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call , callw , return , retlw and retfie instructions or the vectoring to an interrupt address. note: care should be taken when modifying the stkptr while interrupts are enabled. 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x0000 stkptr = 0x1f initial stack configuration: after reset, the stack is empty. the empty stack is initialized so the stack pointer is pointing at 0x1f. if the stack overflow/underflow reset is enabled, the tosh/tosl registers will return ? 0 ?. if the stack overflow/underflow reset is disabled, the tosh/tosl registers will return the contents of stack address 0x0f. 0x1f stkptr = 0x1f stack reset disabled (stvren = 0 ) stack reset enabled (stvren = 1 ) tosh:tosl tosh:tosl
? 2011 microchip technology inc. preliminary ds41569a-page 37 pic16lf1904/6/7 figure 3-6: accessing the stack example 2 figure 3-7: accessing the stack example 3 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x00 this figure shows the stack configuration after the first call or a single interrupt. if a return instruction is executed, the return addre ss will be placed in the program counter and the stack pointer decremented to the empty state (0x1f). tosh:tosl 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 return address 0x06 return address 0x05 return address 0x04 return address 0x03 return address 0x02 return address 0x01 return address 0x00 stkptr = 0x06 after seven call s or six call s and an interrupt, the stack looks like the figure on the left. a series of return instructions will repeatedly place the return addresses into the program counter and pop the stack. tosh:tosl
pic16lf1904/6/7 ds41569a-page 38 preliminary ? 2011 microchip technology inc. figure 3-8: accessing the stack example 4 3.4.2 overflow/underflow reset if the stvren bit in configuration word 2 is programmed to ? 1 ?, the device will be reset if the stack is pushed beyond the sixteenth level or poped beyond the first level, setting the appropriate bits (stkovf or stkunf, respectively) in the pcon register. 3.5 indirect addressing the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the file select registers (fsr). if the fsrn address specifies one of the two indfn registers, the read will return ? 0 ? and the write will not occur (though status bits may be affected). the fsrn register value is created by the pair fsrnh and fsrnl. the fsr registers form a 16-bit address that allows an addressing space with 65536 locations. these locations are divided into three memory regions: ? traditional data memory ? linear data memory ? program flash memory 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x10 when the stack is full, the next call or an interrupt will set the stack pointer to 0x10. this is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. if the stack overflow/underflow reset is enabled, a reset will occur and location 0x00 will not be overwritten. return address return address return address return address return address return address return address return address return address return address return address return address return address return address return address tosh:tosl
? 2011 microchip technology inc. preliminary ds41569a-page 39 pic16lf1904/6/7 figure 3-9: indirect addressing 0x0000 0x0fff traditional fsr address range data memory 0x1000 reserved linear data memory reserved 0x2000 0x29af 0x29b0 0x7fff 0x8000 0xffff 0x0000 0x0fff 0x0000 0x7fff program flash memory note: not all memory regions are completely implemented. consult device memory tables for memory limits. 0x1fff
pic16lf1904/6/7 ds41569a-page 40 preliminary ? 2011 microchip technology inc. 3.5.1 traditional data memory the traditional data memory is a region from fsr address 0x000 to fsr address 0xfff. the addresses correspond to the absolute addresses of all sfr, gpr and common registers. figure 3-10: traditio nal data memory map indirect addressing direct addressing bank select location select 4bsr 6 0 from opcode fsrxl 70 bank select location select 00000 00001 00010 11111 0x00 0x7f bank 0 bank 1 bank 2 bank 31 0 fsrxh 70 0000
? 2011 microchip technology inc. preliminary ds41569a-page 41 pic16lf1904/6/7 3.5.2 linear data memory the linear data memory is the region from fsr address 0x2000 to fsr address 0x29af. this region is a virtual region that points back to the 80-byte blocks of gpr memory in all the banks. unimplemented memory reads as 0x00. use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the fsr beyond one bank will go directly to the gpr memory of the next bank. the 16 bytes of common memory are not included in the linear data memory region. figure 3-11: linear data memory map 3.5.3 program flash memory to make constant data access easier, the entire program flash memory is mapped to the upper half of the fsr address space. when the msb of fsrnh is set, the lower 15 bits are the address in program memory which will be accessed through indf. only the lower 8 bits of each memory location is accessible via indf. writing to the program flash memory cannot be accomplished via the fsr/indf interface. all instructions that access program flash memory via the fsr/indf interface will require one additional instruction cycle to complete. figure 3-12: program flash memory map 7 0 1 7 0 0 location select 0x2000 fsrnh fsrnl 0x020 bank 0 0x06f 0x0a0 bank 1 0x0ef 0x120 bank 2 0x16f 0xf20 bank 30 0xf6f 0x29af 0 7 1 7 0 0 location select 0x8000 fsrnh fsrnl 0x0000 0x7fff 0xffff program flash memory (low 8 bits)
pic16lf1904/6/7 ds41569a-page 42 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 43 pic16lf1904/6/7 4.0 device configuration device configuration consists of configuration word 1 and configuration word 2, code protection and device id. 4.1 configuration words there are several configuration word bits that allow different oscillator and memory protection options. these are implemented as configuration word 1 at 8007h and configuration word 2 at 8008h. note: the debug bit in configuration word 2 is managed automatically by device development tools including debuggers and programmers. for normal device operation, this bit should be maintained as a ' 1 '.
pic16lf1904/6/7 ds41569a-page 44 preliminary ? 2011 microchip technology inc. register 4-1: co nfiguration word 1 u-1 u-1 r/p-1 r/p-1 r/p-1 u-1 ? ?clkouten boren<1:0> ? bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 r/p-1 r/p-1 cp mclre pwrte wdte<1:0> ? fosc<1:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13-12 unimplemented: read as ? 1 ? bit 11 clkouten : clock out enable bit 1 = clkout function is disabled. i/o function on the clkout pin. 0 = clkout function is enabled on the clkout pin bit 10-9 boren<1:0>: brown-out reset enable bits 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 01 = bor controlled by sboren bit of the borcon register 00 = bor disabled bit 8 unimplemented: read as ? 1 ? bit 7 cp : code protection bit 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 6 mclre: mclr /v pp pin function select bit if lvp bit = 1 : this bit is ignored. if lvp bit = 0 : 1 =mclr /v pp pin function is mclr ; weak pull-up enabled. 0 =mclr /v pp pin function is digital input; mclr internally disabled; weak pull-up under control of wpue3 bit. bit 5 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 4-3 wdte<1:0>: watchdog timer enable bit 11 = wdt enabled 10 = wdt enabled while running and disabled in sleep 01 = wdt controlled by the swdten bit in the wdtcon register 00 = wdt disabled bit 2 unimplemented: read as ? 1 ? bit 1-0 fosc<1:0>: oscillator selection bits 00 = intosc oscillator: i/o function on clkin pin 01 = ecl: external clock, low-power mode (0-0.5 mhz): device clock supplied to clkin pin 10 = ecm: external clock, medium-power mode (0.5-4 mhz): device clock supplied to clkin pin 11 = ech: external clock, high-power mode (4-20 mhz): device clock supplied to clkin pin
? 2011 microchip technology inc. preliminary ds41569a-page 45 pic16lf1904/6/7 register 4-2: co nfiguration word 2 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 lvp debug lpbor borv stvren ? bit 13 bit 8 u-1 u-1 u-1 u-1 u-1 u-1 r/p-1 r/p-1 ? ? ? ? ? ?wrt<1:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13 lvp: low-voltage programming enable bit 1 = low-voltage programming enabled 0 = high-voltage on mclr must be used for programming bit 12 debug : in-circuit debugger mode bit 1 = in-circuit debugger disabled, icspclk and icspdat are general purpose i/o pins 0 = in-circuit debugger enabled, icspclk and icspdat are dedicated to the debugger bit 11 lpbor : low-power bor bit 1 = low-power bor is disabled 0 = low-power bor is enabled bit 10 borv: brown-out reset voltage selection bit 1 = brown-out reset voltage set to 1.9v (typical) 0 = brown-out reset voltage set to 2.5v (typical) bit 9 stvren: stack overflow/underflow reset enable bit 1 = stack overflow or underflow will cause a reset 0 = stack overflow or underflow will not cause a reset bit 8-2 unimplemented: read as ? 1 ? bit 1-0 wrt<1:0>: flash memory self-write protection bits 4 kw flash memory ( pic16lf1904 o nly) : 11 = write protection off 10 = 000h to 1ffh write-protected, 200h to fffh may be modified by pmcon control 01 = 000h to 7ffh write-protected, 800h to fffh may be modified by pmcon control 00 = 000h to fffh write-protected, no addresses may be modified by pmcon control 8 kw flash memory ( pic16lf1907 only) : 11 = write protection off 10 = 000h to 1ffh write-protected, 200h to 1fffh may be modified by pmcon control 01 = 000h to fffh write-protected, 1000h to 1fffh may be modified by pmcon control 00 = 000h to 1fffh write-protected, no addresses may be modified by pmcon control
pic16lf1904/6/7 ds41569a-page 46 preliminary ? 2011 microchip technology inc. 4.2 code protection code protection allows the device to be protected from unauthorized access. program memory protection is controlled independently. internal access to the program memory is unaffected by any code protection setting. 4.2.1 program memory protection the entire program memory space is protected from external reads and writes by the cp bit in configuration word 1. when cp = 0 , external reads and writes of program memory are inhibited and a read will return all ? 0 ?s. the cpu can continue to read program memory, regardless of the protection bit settings. writing the program memory is dependent upon the write protection setting. see section 4.3 ?write protection? for more information. 4.3 write protection write protection allows the device to be protected from unintended self-writes. applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. the wrt<1:0> bits in configuration word 2 define the size of the program memory block that is protected. 4.4 user id four memory locations (8000h-8003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are readable and writable during normal execution. see section 10.4 ?user id, device id and configuration word access? for more information on accessing these memory locations. for more information on checksum calculation, see the ? pic16f193x/lf193x/pic16f194x/lf194x/pic16lf 190x memory programming specification ? (ds41397) .
? 2011 microchip technology inc. preliminary ds41569a-page 47 pic16lf1904/6/7 4.5 device id and revision id the memory location 8006h is where the device id and revision id are stored. the upper nine bits hold the device id. the lower five bits hold the revision id. see section 10.4 ?user id, device id and configuration word access? for more information on accessing these memory locations. development tools, such as device programmers and debuggers, may be used to read the device id and revision id. register 4-3: deviceid: device id register rrrrrr dev<8:3> bit 13 bit 8 rrrrrrrr dev<2:0> rev<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?1? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared p = programmable bit bit 13-5 dev<8:0>: device id bits bit 4-0 rev<4:0>: revision id bits these bits are used to identify the revision (see table under dev<8:0> above). device deviceid<13:0> values dev<8:0> rev<4:0> pic16lf1904 10 1100 100 x xxxx pic16lf1906 10 1100 011 x xxxx pic16lf1907 10 1100 010 x xxxx
pic16lf1904/6/7 ds41569a-page 48 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 49 pic16lf1904/6/7 5.0 resets there are multiple ways to reset this device: ? power-on reset (por) ? brown-out reset (bor) ? low-power brown-out reset (lpbor) ?mclr reset ?wdt reset ? reset instruction ? stack overflow ? stack underflow ? programming mode exit to allow v dd to stabilize, an optional power-up timer can be enabled to extend the reset time after a bor or por event. a simplified block diagram of the on-chip reset circuit is shown in figure 5-1 . figure 5-1: simplified block diagram of on-chip reset circuit external reset mclr v dd wdt time-out power-on reset lfintosc pwrt 72 ms pwrten brown-out reset bor reset instruction stack pointer stack overflow/underflow reset sleep mclre enable device reset zero programming mode exit lpbor reset
pic16lf1904/6/7 ds41569a-page 50 preliminary ? 2011 microchip technology inc. 5.1 power-on reset (por) the por circuit holds the device in reset until v dd has reached an acceptable level for minimum operation. slow rising v dd , fast operating speeds or analog performance may require greater than minimum v dd . the pwrt, bor or mclr features can be used to extend the start-up period until all device operation conditions have been met. 5.1.1 power-up timer (pwrt) the power-up timer provides a nominal 64 ms time-out on por or brown-out reset. the device is held in reset as long as pwrt is active. the pwrt delay allows additional time for the v dd to rise to an acceptable level. the power-up timer is enabled by clearing the pwrte bit in configuration word 1. the power-up timer starts after the release of the por and bor. for additional information, refer to application note an607, ?power-up trouble shooting? (ds00607). 5.2 brown-out reset (bor) the bor circuit holds the device in reset when v dd reaches a selectable minimum level. between the por and bor, complete voltage range coverage for execution protection can be implemented. the brown-out reset module has four operating modes controlled by the boren<1:0> bits in configu- ration word 1. the four operating modes are: ? bor is always on ? bor is off when in sleep ? bor is controlled by software ? bor is always off refer to tab le 5 - 1 for more information. the brown-out reset voltage level is selectable by configuring the borv bit in configuration word 2. a v dd noise rejection filter prevents the bor from trig- gering on small events. if v dd falls below v bor for a duration greater than parameter t bordc , the device will reset. see figure 5-2 for more information. table 5-1: bor operating modes 5.2.1 bor is always on when the boren bits of configuration word 1 are set to ? 11 ?, the bor is always on. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is active during sleep. the bor does not delay wake-up from sleep. 5.2.2 bor is off in sleep when the boren bits of configuration word 1 are set to ? 10 ?, the bor is on, except in sleep. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is not active during sleep. the device wake-up will be delayed until the bor is ready. 5.2.3 bor controlled by software when the boren bits of configuration word 1 are set to ? 01 ?, the bor is controlled by the sboren bit of the borcon register. the device start-up is not delayed by the bor ready condition or the v dd level. bor protection begins as soon as the bor circuit is ready. the status of the bor circuit is reflected in the borrdy bit of the borcon register. bor protection is unchanged by sleep. boren<1:0> sboren device mode bor mode device operation upon release of por device operation upon wake- up from sleep 11 x x active waits for bor ready (1) 10 x awake active waits for bor ready sleep disabled 01 1 x active begins immediately 0 disabled begins immediately 00 x x disabled begins immediately note 1: even though this case specifically waits for the bor, the bor is already operating, so there is no delay in start-up.
? 2011 microchip technology inc. preliminary ds41569a-page 51 pic16lf1904/6/7 figure 5-2: brown-out situations register 5-1: borco n: brown-out reset control register r/w-1/u r/w-0/u u-0 u-0 u-0 u-0 u-0 r-q/u sboren borfs ? ? ? ? ?borrdy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 sboren: software brown-out reset enable bit if boren <1:0> in configuration word 1 ? 01 : sboren is read/write, but has no effect on the bor. if boren <1:0> in configuration word 1 = 01 : 1 = bor enabled 0 = bor disabled bit 6 borfs: brown-out reset fast start bit (1) if boren<1:0> = 11 (always on) or boren<1:0> = 00 (always off) borfs is read/write, but has no effect. if boren <1:0> = 10 (disabled in sleep) or boren<1:0> = 01 ( under software control): 1 = band gap is forced on always (covers sleep/wake-up/operating cases) 0 = band gap operates normally, and may turn off bit 5-1 unimplemented: read as ? 0 ? bit 0 borrdy: brown-out reset circuit ready status bit 1 = the brown-out reset circuit is active 0 = the brown-out reset circuit is inactive t pwrt (1) v bor v dd internal reset v bor v dd internal reset t pwrt (1) < t pwrt t pwrt (1) v bor v dd internal reset note 1: t pwrt delay only if pwrte bit is programmed to ? 0 ?.
pic16lf1904/6/7 ds41569a-page 52 preliminary ? 2011 microchip technology inc. 5.3 low-power brown-out reset (lpbor) the low-power brown-out reset (lpbor) is an essential part of the reset subsystem. refer to figure 5-1 to see how the bor interacts with other modules. the lpbor is used to monitor the external v dd pin. when too low of a voltage is detected, the device is held in reset. when this occurs, a register bit (bor ) is changed to indicate that a bor reset has occurred. the same bit is set for both the bor and the lpbor. refer to register 5-2 . 5.3.1 enabling lpbor the lpbor is controlled by the l pbor bit of configuration word 2. when the device is erased, the lpbor module defaults to disabled. 5.3.1.1 lpbor module output the output of the lpbor module is a signal indicating whether or not a reset is to be asserted. this signal is to be or?d together with the reset signal of the bor module to provide the generic bor signal, which goes to the pcon register and to the power control block. 5.4 mclr the mclr is an optional external input that can reset the device. the mclr function is controlled by the mclre bit of configuration word 1 and the lvp bit of configuration word 2 ( ta b l e 5 - 2 ). 5.4.1 mclr enabled when mclr is enabled and the pin is held low, the device is held in reset. the mclr pin is connected to v dd through an internal weak pull-up. the device has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. 5.4.2 mclr disabled when mclr is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. see section 11.5 ?porte regis- ters? for more information. 5.5 watchdog timer (wdt) reset the watchdog timer generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the to and pd bits in the status register are changed to indicate the wdt reset. see section 9.0 ?watchdog timer? for more information. 5.6 reset instruction a reset instruction will cause a device reset. the ri bit in the pcon register will be set to ? 0 ?. see ta b l e 5 - 4 for default conditions after a reset instruction has occurred. 5.7 stack overflow/underflow reset the device can reset when the stack overflows or underflows. the stkovf or stkunf bits of the pcon register indicate the reset condition. these resets are enabled by setting the stvren bit in configuration word 2. see section 5.7 ?stack overflow/underflow reset? for more information. 5.8 programming mode exit upon exit of programming mode, the device will behave as if a por had just occurred. 5.9 power-up timer the power-up timer optionally delays device execution after a bor or por event. this timer is typically used to allow v dd to stabilize before allowing the device to start running. the power-up timer is controlled by the pwrte bit of configuration word 1. 5.10 start-up sequence upon the release of a por or bor, the following must occur before the device will begin executing: 1. power-up timer runs to completion (if enabled). 2. oscillator start-up timer runs to completion (if required for oscillator source). 3. mclr must be released (if enabled). the total time-out will vary based on oscillator configu- ration and power-up timer configuration. see section 6.0 ?oscillator module? for more informa- tion. the power-up timer and oscillator start-up timer run independently of mclr reset. if mclr is kept low long enough, the power-up timer and oscillator start-up timer will expire. upon bringing mclr high, the device will begin execution immediately (see figure 5-3 ). this is useful for testing purposes or to synchronize more than one device operating in parallel. table 5-2: mclr configuration mclre lvp mclr 00 disabled 10 enabled x1 enabled note: a reset does not drive the mclr pin low.
? 2011 microchip technology inc. preliminary ds41569a-page 53 pic16lf1904/6/7 figure 5-3: reset start-up sequence t ost t mclr t pwrt v dd internal por power-up timer mclr internal reset oscillator modes oscillator start-up timer oscillator f osc internal oscillator oscillator f osc external clock (ec) clkin f osc external crystal
pic16lf1904/6/7 ds41569a-page 54 preliminary ? 2011 microchip technology inc. 5.11 determining the cause of a reset upon any reset, multiple bits in the status and pcon registers are updated to indicate the cause of the reset. ta b l e 5 - 3 and tab le 5 - 4 show the reset conditions of these registers. table 5-3: reset status bits and their significance table 5-4: reset condition for special registers (2) stkovf stkunf rwdt rmclr ri por bor to pd condition 0 0 1 1 10 x11 power-on reset 0 0 1 1 10 x0x illegal, to is set on por 0 0 1 1 10 xx0 illegal, pd is set on por 0 0 u 1 1u 011 brown-out reset u u 0 u uu u0u wdt reset u u u u uu u00 wdt wake-up from sleep u u u u uu u10 interrupt wake-up from sleep u u u 0 uu uuu mclr reset during normal operation u u u 0 uu u10 mclr reset during sleep u u u u 0 u u u u reset instruction executed 1 u u u uu uuu stack overflow reset (stvren = 1 ) u 1 u u uu uuu stack underflow reset (stvren = 1 ) condition program counter status register pcon register power-on reset 0000h ---1 1000 00-1 110x mclr reset during normal operation 0000h ---u uuuu uu-u 0uuu mclr reset during sleep 0000h ---1 0uuu uu-u 0uuu wdt reset 0000h ---0 uuuu uu-0 uuuu wdt wake-up from sleep pc + 1 ---0 0uuu uu-u uuuu brown-out reset 0000h ---1 1uuu 00-1 11u0 interrupt wake-up from sleep pc + 1 (1) ---1 0uuu uu-u uuuu reset instruction executed 0000h ---u uuuu uu-u u0uu stack overflow reset (stvren = 1 ) 0000h ---u uuuu 1u-u uuuu stack underflow reset (stvren = 1 ) 0000h ---u uuuu u1-u uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and global enable bit (gie) is set, the return address is pushed on the stack and pc is loaded with the interrupt vector (0004h) after execution of pc + 1. 2: if a status bit is not implemented, that bit will be read as ? 0 ?.
? 2011 microchip technology inc. preliminary ds41569a-page 55 pic16lf1904/6/7 5.12 power control (pcon) register the power control (pcon) register contains flag bits to differentiate between a: ? power-on reset (por ) ? brown-out reset (bor ) ? reset instruction reset (ri ) ?mclr reset (rmclr ) ? watchdog timer reset (rwdt ) ? stack underflow reset (stkunf) ? stack overflow reset (stkovf) the pcon register bits are shown in register 5-2 . register 5-2: pcon: power control register r/w/hs-0/q r/w/hs-0/q u-0 r/w/hc-1/q r/w/ hc-1/q r/w/hc-1/q r/w/hc-q/u r/w/hc-q/u stkovf stkunf ? r wdt rmclr ri por bor bit 7 bit 0 legend: hc = bit is cleared by hardware hs = bit is set by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 stkovf: stack overflow flag bit 1 = a stack overflow occurred 0 = a stack overflow has not occurred or set to ? 0 ? by firmware bit 6 stkunf: stack underflow flag bit 1 = a stack underflow occurred 0 = a stack underflow has not occurred or set to ? 0 ? by firmware bit 5 unimplemented: read as ? 0 ? bit 4 r wdt : watchdog timer reset flag bit 1 = a watchdog timer reset has not occurred or set to ? 1 ? by firmware 0 = a watchdog timer reset has occurred (set to ? 0 ? in hardware when a watchdog timer reset) bit 3 rmclr : mclr reset flag bit 1 = a mclr reset has not occurred or set to ? 1 ? by firmware 0 = a mclr reset has occurred (set to ? 0 ? in hardware when a mclr reset occurs) bit 2 ri : reset instruction flag bit 1 = a reset instruction has not been executed or set to ? 1 ? by firmware 0 = a reset instruction has been executed (set to ? 0 ? in hardware upon executing a reset instruction) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a power-on reset or brown-out reset occurs)
pic16lf1904/6/7 ds41569a-page 56 preliminary ? 2011 microchip technology inc. table 5-5: summary of registers associated with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page borcon sboren borfs ? ? ? ? ? borrdy 51 pcon stkovf stkunf ?rwdt rmclr ri por bor 55 status ? ? ?to pd z dc c 25 wdtcon ? ? wdtps<4:0> swdten 83 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by resets.
? 2011 microchip technology inc. preliminary ds41569a-page 57 pic16lf1904/6/7 6.0 oscillator module 6.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. figure 6-1 illustrates a block diagram of the oscillator module. clock sources can be supplied from external clock circuits. in addition, the system clock source can be supplied from one of two internal oscillators, with a choice of speeds selectable via software. additional clock features include: ? selectable system clock source between external or internal sources via software. ? fast start-up oscillator allows internal circuits to power up and stabilize before switching to the 16 mhz hfintosc the oscillator module can be configured in one of the following clock modes: 1. ecl ? external clock low-power mode (0 mhz to 0.5 mhz) 2. ecm ? external clock medium-power mode (0.5 mhz to 4 mhz) 3. ech ? external clock high-power mode (4 mhz to 20 mhz) 4. intosc ? internal oscillator (31 khz to 16 mhz). clock source modes are selected by the fosc<1:0> bits in the configuration word 1. the fosc bits determine the type of oscillator that will be used when the device is first powered. the ec clock mode relies on an external logic level signal as the device clock source. the intosc internal oscillator block produces a low and high-frequency clock source, designated lfintosc and hfintosc (see internal oscillator block, figure 6-1 ). a wide selection of device clock frequencies may be derived from these two clock sources.
pic16lf1904/6/7 ds41569a-page 58 preliminary ? 2011 microchip technology inc. figure 6-1: simplified pic ? mcu clock source block diagram clkin clkin ec t1cki/ t1oso t1osi secondary oscillator (t1osc) 16 mhz primary osc start-up osc lf-intosc (31 khz) intosc divide circuit ircf<3:0> intosc primary clock secondary clock clock switch mux 01 00 1x low power mode event switch (scs<1:0>) 2 4 secondary oscillator internal oscillator hf-16 mhz hf-4 mhz hf-2 mhz hf-1 mhz hf-500 khz hf-250 khz hf-125 khz hf-62.5 khz hf-31.25 khz lf-31 khz hf-8 mhz internal oscillator mux 4 1111 1110 1101 1100 1011 1010/ 0111 1001/ 0110 1000/ 0101 0100 0011 0010 0001 0000 /1 /2 /4 /8 /16 /32 /64 /128 /256 /512 start-up control logic
? 2011 microchip technology inc. preliminary ds41569a-page 59 pic16lf1904/6/7 6.2 clock source types clock sources can be classified as external or internal. external clock sources rely on external circuitry for the clock source to function. an example is: oscillator mod- ule (ec mode) circuit. internal clock sources are contained internally within the oscillator module. the internal oscillator block has two internal oscillators that are used to generate the internal system clock sources: the 16 mhz high-frequency internal oscillator and the 31 khz low-frequency internal oscillator (lfintosc). the system clock can be selected between external or internal clock sources via the system clock select (scs) bits in the osccon register. see section 6.3 ?clock switching? for additional information. 6.2.1 external clock sources an external clock source can be used as the device system clock by performing one of the following actions: ? program the fosc<1:0> bits in the configuration word 1 to select an external clock source that will be used as the default system clock upon a device reset. ? write the scs<1:0> bits in the osccon register to switch the system clock source to: - secondary oscillator during run-time, or - an external clock source determined by the value of the fosc bits. see section 6.3 ?clock switching? for more informa- tion. 6.2.1.1 ec mode the external clock (ec) mode allows an externally generated logic level signal to be the system clock source. when operating in this mode, an external clock source is connected to the clkin input. clkout is available for general purpose i/o or clkout. figure 6-2 shows the pin connections for ec mode. ec mode has 3 power modes to select from through configuration word 1: ? high power, 4-20 mhz (fosc = 11 ) ? medium power, 0.5-4 mhz (fosc = 10 ) ? low power, 0-0.5 mhz (fosc = 01 ) the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 6-2: external clock (ec) mode operation clkin clkout clock from ext. system pic ? mcu f osc /4 or i/o (1) note 1: output depends upon clkouten bit of the configuration word 1.
pic16lf1904/6/7 ds41569a-page 60 preliminary ? 2011 microchip technology inc. 6.2.1.2 secondary oscillator the secondary oscillator is a separate crystal oscillator that is associated with the timer1 peripheral. it is opti- mized for timekeeping operations with a 32.768 khz crystal connected between the t1cki/t1oso and t1osi device pins. the secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. refer to section 6.3 ?clock switching? for more information. figure 6-3: quartz crystal operation (secondary oscillator) 6.2.2 internal clock sources the device may be configured to use the internal oscil- lator block as the system clock by performing one of the following actions: ? program the fosc<1:0> bits in configuration word 1 to select the intosc clock source, which will be used as the default system clock upon a device reset. ? write the scs<1:0> bits in the osccon register to switch the system clock source to the internal oscillator during run-time. see section 6.3 ?clock switching? for more information. in intosc mode, clkin is available for general purpose i/o. clkout is available for general purpose i/o or clkout. the function of the clkout pin is determined by the state of the clkouten bit in configuration word 1. the internal oscillator block has two independent oscillators that provides the internal system clock source. 1. the hfintosc (high-frequency internal oscillator) is factory calibrated and operates at 16 mhz. 2. the lfintosc (low-frequency internal oscillator) is uncalibrated and operates at 31 khz. 6.2.2.1 hfintosc the high-frequency internal oscillator (hfintosc) is a factory calibrated 16 mhz internal clock source. the output of the hfintosc connects to a postscaler and multiplexer (see figure 6-1 ). the frequency derived from the hfintosc can be selected via software using the ircf<3:0> bits of the osccon register. see section 6.2.2.4 ?internal oscillator clock switch timing? for more information. the hfintosc is enabled by: ? configure the ircf<3:0> bits of the osccon register for the desired hf frequency, and ?fosc<1:0> = 11 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ?. the high-frequency internal oscillator ready bit (hfiofr) of the oscstat register indicates when the hfintosc is running and can be utilized. the high-frequency internal oscillator status stable bit (hfiofs) of the oscstat register indicates when the hfintosc is running within 0.5% of its final value. note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) ? tb097, ? interfacing a micro crystal ms1v-t1k 32.768 khz tuning fork crystal to a pic16f690/ss ? (ds91097) ? an1288, ? design practices for low-power external oscillators ? (ds01288) c1 c2 32.768 khz t1cki/t1oso to internal logic pic ? mcu crystal t1osi quartz
? 2011 microchip technology inc. preliminary ds41569a-page 61 pic16lf1904/6/7 6.2.2.2 lfintosc the low-frequency internal oscillator (lfintosc) is an uncalibrated 31 khz internal clock source. the output of the lfintosc connects to a postscaler and multiplexer (see figure 6-1 ). select 31 khz, via software, using the ircf<3:0> bits of the osccon register. see section 6.2.2.4 ?internal oscillator clock switch timing? for more information. the lfintosc is also the frequency for the power-up timer (pwrt) and watchdog timer (wdt). the lfintosc is enabled by selecting 31 khz (ircf<3:0> bits of the osccon register = 000 ) as the system clock source (scs bits of the osccon register = 1x ), or when any of the following are enabled: ? configure the ircf<3:0> bits of the osccon register for the desired lf frequency, and ?fosc<1:0> = 01 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ? peripherals that use the lfintosc are: ? power-up timer (pwrt) ? watchdog timer (wdt) the low-frequency internal oscillator ready bit (lfiofr) of the oscstat register indicates when the lfintosc is running and can be utilized. 6.2.2.3 internal oscillator frequency selection the system clock speed can be selected via software using the internal oscillator frequency select bits ircf<3:0> of the osccon register. the output of the 16 mhz hfintosc and 31 khz lfintosc connects to a postscaler and multiplexer (see figure 6-1 ). the internal oscillator frequency select bits ircf<3:0> of the osccon register select the frequency output of the internal oscillators. one of the following frequencies can be selected via software: ?16 mhz ?8 mhz ?4 mhz ?2 mhz ?1 mhz ? 500 khz (default after reset) ? 250 khz ? 125 khz ? 62.5 khz ? 31.25 khz ? 31 khz (lfintosc) the ircf<3:0> bits of the osccon register allow duplicate selections for some frequencies. these dupli- cate choices can offer system design trade-offs. lower power consumption can be obtained when changing oscillator sources for a given frequency. faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 6.2.2.4 internal oscillator clock switch timing when switching between the hfintosc and the lfintosc, the new oscillator may already be shut down to save power (see figure 6-4 ). if this is the case, there is a delay after the ircf<3:0> bits of the osccon register are modified before the frequency selection takes place. the oscstat register will reflect the current active status of the hfintosc and lfintosc oscillators. the sequence of a frequency selection is as follows: 1. ircf<3:0> bits of the osccon register are modified. 2. if the new clock is shut down, a clock start-up delay is started. 3. clock switch circuitry waits for a falling edge of the current clock. 4. the current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. the new clock is now active. 6. the oscstat register is updated as required. 7. clock switch is complete. see figure 6-4 for more details. if the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. clock switching time delays are shown in table 6-1 . start-up delay specifications are located in the oscillator tables of section 22.0 ?electrical specifications? . note: following any reset, the ircf<3:0> bits of the osccon register are set to ? 0111 ? and the frequency selection is set to 500 khz. the user can modify the ircf bits to select a different frequency.
pic16lf1904/6/7 ds41569a-page 62 preliminary ? 2011 microchip technology inc. figure 6-4: internal oscillator switch timing hfintosc lfintosc ircf <3:0> system clock hfintosc lfintosc ircf <3:0> system clock ?? 0 ?? 0 ?? 0 ?? 0 start-up time 2-cycle sync running 2-cycle sync running hfintosc lfintosc (wdt disabled) hfintosc lfintosc (wdt enabled) lfintosc hfintosc ircf <3:0> system clock = 0 ? 0 start-up time 2-cycle sync running lfintosc hfintosc lfintosc turns off unless wdt is enabled
? 2011 microchip technology inc. preliminary ds41569a-page 63 pic16lf1904/6/7 6.3 clock switching the system clock source can be switched between external and internal clock sources via software using the system clock select (scs) bits of the osccon register. the following clock sources can be selected using the scs bits: ? default system oscillator determined by fosc bits in configuration word 1 ? secondary oscillator 32 khz crystal ? internal oscillator block (intosc) 6.3.1 system clock select (scs) bits the system clock select (scs) bits of the osccon register selects the system clock source that is used for the cpu and peripherals. ? when the scs bits of the osccon register = 00 , the system clock source is determined by value of the fosc<1:0> bits in the configuration word 1. ? when the scs bits of the osccon register = 01 , the system clock source is the secondary oscillator. ? when the scs bits of the osccon register = 1x , the system clock source is chosen by the internal oscillator frequency selected by the ircf<3:0> bits of the osccon register. after a reset, the scs bits of the osccon register are always cleared. when switching between clock sources, a delay is required to allow the new clock to stabilize. these oscil- lator delays are shown in table 6-1 . 6.3.2 oscillator start-up time-out status (osts) bit the oscillator start-up time-out status (osts) bit of the oscstat register indicates whether the system clock is running from the external clock source, as defined by the fosc<1:0> bits in the configuration word 1, or from the internal clock source. the ost does not reflect the status of the secondary oscillator. 6.3.3 secondary oscillator the secondary oscillator is a separate crystal oscillator associated with the timer1 peripheral. it is optimized for timekeeping operations with a 32.768 khz crystal connected between the t1osi and t1cki/t1oso device pins. the secondary oscillator is enabled using the t1oscen control bit in the t1con register. see section 17.0 ?timer1 module with gate control? for more information about the timer1 peripheral. 6.3.4 secondary oscillator ready (t1oscr) bit the user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. the secondary oscillator ready (t1oscr) bit of the oscstat register indicates whether the secondary oscillator is ready to be used. after the t1oscr bit is set, the scs bits can be configured to select the secondary oscillator.
pic16lf1904/6/7 ds41569a-page 64 preliminary ? 2011 microchip technology inc. 6.4 oscillator control registers register 6-1: osccon: os cillator control register u-0 r/w-0/0 r/w-1/1 r/w-1/1 r/w-1/1 u-0 r/w-0/0 r/w-0/0 ? ircf<3:0> ? scs<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-3 ircf<3:0>: internal oscillator frequency select bits 000x =31khz lf 001x =31.25khz 0100 =62.5khz 0101 =125khz 0110 =250khz 0111 = 500 khz (default upon reset) 1000 =125khz (1) 1001 =250khz (1) 1010 =500khz (1) 1011 =1mhz 1100 =2mhz 1101 =4mhz 1110 =8mhz 1111 =16mhz bit 2 unimplemented: read as ? 0 ? bit 1-0 scs<1:0>: system clock select bits 1x = internal oscillator block 01 = secondary oscillator 00 = clock determined by fosc<1:0> in configuration word 1. note 1: duplicate frequency derived from hfintosc.
? 2011 microchip technology inc. preliminary ds41569a-page 65 pic16lf1904/6/7 table 6-1: summary of registers asso ciated with clock sources table 6-2: summary of configura tion word with clock sources register 6-2: oscstat: oscillator status register r-1/q u-0 r-q/q r-0/q u-0 u-0 r-0/0 r-0/q t1oscr ? osts hfiofr ? ? lfiofr hfiofs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = conditional bit 7 t1oscr: timer1 oscillator ready bit if t1oscen = 1 : 1 = timer1 oscillator is ready 0 = timer1 oscillator is not ready if t1oscen = 0 : 1 = timer1 clock source is always ready bit 6 unimplemented: read as ? 0 ? bit 5 osts: oscillator start-up time-out status bit 1 = running from the external clock source (ec) 0 = running from an internal oscillator (fosc<1:0> = 00 ) bit 4 hfiofr: high-frequency internal oscillator ready bit 1 = hfintosc is ready 0 = hfintosc is not ready bit 3-2 unimplemented: read as ? 0 ? bit 1 lfiofr: low-frequency internal oscillator ready bit 1 = lfintosc is ready 0 = lfintosc is not ready bit 0 hfiofs: high-frequency internal oscillator stable bit 1 = hfintosc 16 mhz oscillator is stable and is driving the intosc 0 = hfintosc 16 mhz oscillator is not stable, the start-up oscillator is driving intosc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon ? ircf<3:0> ?scs<1:0> 64 oscstat t1oscr ? osts hfiofr ? ? lfiofr hfiofs 65 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ? tmr1on 151 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? ? ?clkouten boren<1:0> ? 44 7:0 cp mclre pwrte wdte<1:0> ? fosc<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources.
pic16lf1904/6/7 ds41569a-page 66 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 67 pic16lf1904/6/7 7.0 interrupts the interrupt feature allows certain events to preempt normal program flow. firmware is used to determine the source of the interrupt and act accordingly. some interrupts can be configured to wake the mcu from sleep mode. this chapter contains the following information for interrupts: ? operation ? interrupt latency ? interrupts during sleep ?int pin ? automatic context saving many peripherals produce interrupts. refer to the cor- responding chapters for details. a block diagram of the interrupt logic is shown in figure 7.1 . figure 7-1: interrupt logic tmr0if tmr0ie intf inte iocif iocie interrupt to cpu wake-up (if in sleep mode) gie (tmr1if) pir1<0> pirn<7> pien<7> peie peripheral interrupts (tmr1if) pir1<0>
pic16lf1904/6/7 ds41569a-page 68 preliminary ? 2011 microchip technology inc. 7.1 operation interrupts are disabled upon any device reset. they are enabled by setting the following bits: ? gie bit of the intcon register ? interrupt enable bit(s) for the specific interrupt event(s) ? peie bit of the intcon register (if the interrupt enable bit of the interrupt event is contained in the pie1 and pie2 registers) the intcon, pir1 and pir2 registers record individ- ual interrupts via interrupt flag bits. interrupt flag bits will be set, regardless of the status of the gie, peie and individual interrupt enable bits. the following events happen when an interrupt event occurs while the gie bit is set: ? current prefetched instruction is flushed ? gie bit is cleared ? current program counter (pc) is pushed onto the stack ? critical registers are automatically saved to the shadow registers (see section 7.5 ?automatic context saving? ) ? pc is loaded with the interrupt vector 0004h the firmware within the interrupt service routine (isr) should determine the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr to avoid repeated interrupts. because the gie bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. the retfie instruction exits the isr by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the gie bit. for additional information on a specific interrupt?s operation, refer to its peripheral chapter. 7.2 interrupt latency interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. the latency for synchronous interrupts is 3 or 4 instruction cycles. for asynchronous interrupts, the latency is 3 to 5 instruction cycles, depending on when the interrupt occurs. see figure 7-2 and figure 7.3 for more details. note 1: individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: all interrupts will be ignored while the gie bit is cleared. any interrupt occurring while the gie bit is clear will be serviced when the gie bit is set again.
? 2011 microchip technology inc. preliminary ds41569a-page 69 pic16lf1904/6/7 figure 7-2: interrupt latency q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 clkin clkout pc 0004h 0005h pc inst(0004h) nop gie q1 q2 q3 q4 q1 q2 q3 q4 1 cycle instruction at pc pc inst(0004h) nop 2 cycle instruction at pc fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc execute interrupt inst(pc) interrupt sampled during q1 inst(pc) pc-1 pc+1 nop pc new pc/ pc+1 0005h pc-1 pc+1/fsr addr 0004h nop interrupt gie interrupt inst(pc) nop nop fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc interrupt inst(pc) nop nop nop inst(0005h) execute execute execute
pic16lf1904/6/7 ds41569a-page 70 preliminary ? 2011 microchip technology inc. figure 7-3: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 clkin clkout int pin intf gie instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc + 1) inst (pc ? 1) inst (0004h) dummy cycle inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-5 t cy . synchronous latency = 3-4 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout not available in all oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 22.0 ?electrical specifications? ? . 5: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (5) (1)
? 2011 microchip technology inc. preliminary ds41569a-page 71 pic16lf1904/6/7 7.3 interrupts during sleep some interrupts can be used to wake from sleep. to wake from sleep, the peripheral must be able to operate without the system clock. the interrupt source must have the appropriate interrupt enable bit(s) set prior to entering sleep. on waking from sleep, if the gie bit is also set, the processor will branch to the interrupt vector. otherwise, the processor will continue executing instructions after the sleep instruction. the instruction directly after the sleep instruction will always be executed before branching to the isr. refer to section 8.0 ?power-down mode (sleep)? for more details. 7.4 int pin the int pin can be used to generate an asynchronous edge-triggered interrupt. this interrupt is enabled by setting the inte bit of the intcon register. the intedg bit of the option_reg register determines on which edge the interrupt will occur. when the intedg bit is set, the rising edge will cause the interrupt. when the intedg bit is clear, the falling edge will cause the interrupt. the intf bit of the intcon register will be set when a valid edge appears on the int pin. if the gie and inte bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 automatic context saving upon entering an interrupt, the return pc address is saved on the stack. additionally, the following registers are automatically saved in the shadow registers: ? w register ? status register (except for to and pd ) ? bsr register ? fsr registers ? pclath register upon exiting the interrupt service routine, these regis- ters are automatically restored. any modifications to these registers during the isr will be lost. if modifica- tions to any of these registers are desired, the corre- sponding shadow register should be modified and the value will be restored when exiting the isr. the shadow registers are available in bank 31 and are readable and writable. depending on the user?s appli- cation, other registers may also need to be saved.
pic16lf1904/6/7 ds41569a-page 72 preliminary ? 2011 microchip technology inc. 7.6 interrupt control registers 7.6.1 intcon register the intcon register is a readable and writable register, which contains the various enable and flag bits for tmr0 register overflow, interrupt-on-change and external int pin interrupts. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 7-1: intcon: interrupt control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 gie peie tmr0ie inte iocie tmr0if intf iocif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 gie: global interrupt enable bit 1 = enables all active interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all active peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie: timer0 overflow interrupt enable bit 1 = enables the timer0 interrupt 0 = disables the timer0 interrupt bit 4 inte: int external interrupt enable bit 1 = enables the int external interrupt 0 = disables the int external interrupt bit 3 iocie: interrupt-on-change interrupt enable bit 1 = enables the interrupt-on-change interrupt 0 = disables the interrupt-on-change interrupt bit 2 tmr0if: timer0 overflow interrupt flag bit 1 = tmr0 register has overflowed 0 = tmr0 register did not overflow bit 1 intf: int external interrupt flag bit 1 = the int external interrupt occurred 0 = the int external interrupt did not occur bit 0 iocif: interrupt-on-change interrupt flag bit 1 = when at least one of the interrupt-on-change pins changed state 0 = none of the interrupt-on-change pins have changed state
? 2011 microchip technology inc. preliminary ds41569a-page 73 pic16lf1904/6/7 7.6.2 pie1 register the pie1 register contains the interrupt enable bits, as shown in register 7-2 . note: bit peie of the intcon register must be set to enable any peripheral interrupt. register 7-2: pie1: peripheral interrupt enable register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 r/w-0/0 tmr1gie adie rcie txie ? ? ?tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 tmr1gie: timer1 gate interrupt enable bit 1 = enables the timer1 gate acquisition interrupt 0 = disables the timer1 gate acquisition interrupt bit 6 adie: a/d converter (adc) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5 rcie: usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie: usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3-1 unimplemented: read as ? 0 ? bit 0 tmr1ie: timer1 overflow interrupt enable bit 1 = enables the timer1 overflow interrupt 0 = disables the timer1 overflow interrupt .
pic16lf1904/6/7 ds41569a-page 74 preliminary ? 2011 microchip technology inc. 7.6.3 pie2 register the pie2 register contains the interrupt enable bits, as shown in register 7-3 . note: bit peie of the intcon register must be set to enable any peripheral interrupt. register 7-3: pie2: peripheral interrupt enable register 2 u-0 u-0 u-0 u-0 u-0 r/w-0/0 u-0 u-0 ? ? ? ? ? lcdie ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2 lcdie: lcd module interrupt enable bit 1 = enables the lcd module interrupt 0 = disables the lcd module interrupt bit 1-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. preliminary ds41569a-page 75 pic16lf1904/6/7 7.6.4 pir1 register the pir1 register contains the interrupt flag bits, as shown in register 7-4 . note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 7-4: pir1: peripheral interrupt request register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 r/w-0/0 tmr1gif adif rcif txif ? ? ?tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 tmr1gif: timer1 gate interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6 adif: a/d converter interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5 rcif: usart receive interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 txif: usart transmit interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 3-1 unimplemented: read as ? 0 ? bit 0 tmr1if: timer1 overflow interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending
pic16lf1904/6/7 ds41569a-page 76 preliminary ? 2011 microchip technology inc. 7.6.5 pir2 register the pir2 register contains the interrupt flag bits, as shown in register 7-5 . note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 7-5: pir2: peripheral interrupt request register 2 u-0 u-0 u-0 u-0 u-0 r/w-0/0 u-0 u-0 ? ? ? ? ? lcdif ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2 lcdif: lcd module interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 1-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. preliminary ds41569a-page 77 pic16lf1904/6/7 table 7-1: summary of registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 option_reg wpuen intedg t0cs t0se psa ps<2:0> 141 pie1 tmr1gie adie rcie txie ? ? ?tmr1ie 73 pie2 ? ? ? ? ? lcdie ? ? 74 pir1 tmr1gif adif rcif txif ? ? ?tmr1if 75 pir2 ? ? ? ? ? lcdif ? ? 76 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by interrupts.
pic16lf1904/6/7 ds41569a-page 78 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 79 pic16lf1904/6/7 8.0 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. upon entering sleep mode, the following conditions exist: 1. wdt will be cleared but keeps running, if enabled for operation during sleep. 2. pd bit of the status register is cleared. 3. to bit of the status register is set. 4. cpu clock is disabled. 5. 31 khz lfintosc is unaffected and peripherals that operate from it may continue operation in sleep. 6. secondary oscillator is unaffected and peripher- als that operate from it may continue operation in sleep. 7. adc is unaffected, if the dedicated frc clock is selected. 8. capacitive sensing oscillator is unaffected. 9. i/o ports maintain the status they had before sleep was executed (driving high, low or high-impedance). 10. resets other than wdt are not affected by sleep mode. refer to individual chapters for more details on peripheral operation during sleep. to minimize current consumption, the following condi- tions should be considered: ? i/o pins should not be floating ? external circuitry sinking current from i/o pins ? internal circuitry sourcing current from i/o pins ? current draw from pins with internal weak pull-ups ? modules using 31 khz lfintosc ? modules using secondary oscillator i/o pins that are high-impedance inputs should be pulled to v dd or v ss externally to avoid switching cur- rents caused by floating inputs. examples of internal circuitry that might be sourcing current include the fvr module. see 13.0 ?fixed volt- age reference (fvr)? for more information. 8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin, if enabled 2. bor reset, if enabled 3. por reset 4. watchdog timer, if enabled 5. any external interrupt 6. interrupts by peripherals capable of running dur- ing sleep (see individual peripheral for more information) the first three events will cause a device reset. the last three events are considered a continuation of pro- gram execution. to determine whether a device reset or wake-up event occurred, refer to section 5.11, determining the cause of a reset . when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. wake-up will occur regardless of the state of the gie bit. if the gie bit is disabled, the device continues execution at the instruction after the sleep instruction. if the gie bit is enabled, the device executes the instruction after the sleep instruction, the device will call the interrupt ser- vice routine. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up.
pic16lf1904/6/7 ds41569a-page 80 preliminary ? 2011 microchip technology inc. 8.1.1 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction - sleep instruction will execute as a nop . - wdt and wdt prescaler will not be cleared -to bit of the status register will not be set -pd bit of the status register will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction - sleep instruction will be completely exe- cuted - device will immediately wake-up from sleep - wdt and wdt prescaler will be cleared -to bit of the status register will be set -pd bit of the status register will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . figure 8-1: wake-up from sleep through interrupt table 8-1: summary of registers as sociated with power-down mode q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 clkin (1) clkout (2) interrupt flag gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (1) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle pc + 2 note 1: gie = 1 assumed. in this case after wake-up, the processor calls the isr at 0004h. if gie = 0 , execution will continue in-line. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 iocbf iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 118 iocbn iocbn7 iocbn6 iocbn5 iocbn 4 iocbn3 iocbn2 iocbn1 iocbn0 118 iocbp iocbp7 iocbp6 iocbp5 iocbp4 iocbp3 iocbp2 iocbp1 iocbp0 118 pie1 tmr1gie adie rcie txie ? ? ?tmr1ie 73 pie2 ? ? ? ? ?lcdie ? ? 74 pir1 tmr1gif adif rcif txif ? ? ? tmr1if 75 pir2 ? ? ? ? ? lcdif ? ? 76 status ? ? ?to pd zdcc 25 wdtcon ? ? wdtps<4:0> swdten 83 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used in power-down mode.
? 2011 microchip technology inc. preliminary ds41569a-page 81 pic16lf1904/6/7 9.0 watchdog timer the watchdog timer is a system timer that generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the watchdog timer is typically used to recover the system from unexpected events. the wdt has the following features: ? independent clock source ? multiple operating modes - wdt is always on - wdt is off when in sleep - wdt is controlled by software - wdt is always off ? configurable time-out period is from 1 ms to 256 seconds (typical) ? multiple reset conditions ? operation during sleep figure 9-1: watchdog ti mer block diagram lfintosc 23-bit programmable prescaler wdt wdt time-out wdtps<4:0> swdten sleep wdte<1:0> = 11 wdte<1:0> = 01 wdte<1:0> = 10
pic16lf1904/6/7 ds41569a-page 82 preliminary ? 2011 microchip technology inc. 9.1 independent clock source the wdt derives its time base from the 31 khz lfintosc internal oscillator. time intervals in this chapter are based on a nominal interval of 1ms. see section 22.0 ?electrical specifications? for the lfintosc tolerances. 9.2 wdt operating modes the watchdog timer module has four operating modes controlled by the wdte<1:0> bits in configuration word 1. see ta b l e 9 - 1 . 9.2.1 wdt is always on when the wdte bits of configuration word 1 are set to ? 11 ?, the wdt is always on. wdt protection is active during sleep. 9.2.2 wdt is off in sleep when the wdte bits of configuration word 1 are set to ? 10 ?, the wdt is on, except in sleep. wdt protection is not active during sleep. 9.2.3 wdt controlled by software when the wdte bits of configuration word 1 are set to ? 01 ?, the wdt is controlled by the swdten bit of the wdtcon register. wdt protection is unchanged by sleep. see table 9-1 for more details. table 9-1: wdt operating modes 9.3 time-out period the wdtps bits of the wdtcon register set the time-out period from 1 ms to 256 seconds (nominal). after a reset, the default time-out period is 2 seconds. 9.4 clearing the wdt the wdt is cleared when any of the following condi- tions occur: ?any reset ? clrwdt instruction is executed ? device enters sleep ? device wakes up from sleep ? oscillator fail event ? wdt is disabled ? oscillator start-up timer (ost) is running see table 9-2 for more information. 9.5 operation during sleep when the device enters sleep, the wdt is cleared. if the wdt is enabled during sleep, the wdt resumes counting. when the device exits sleep, the wdt is cleared again. the wdt remains clear until the ost, if enabled, completes. see section 6.0 ?oscillator module? for more information on the ost. when a wdt time-out occurs while the device is in sleep, no reset is generated. instead, the device wakes up and resumes operation. the to and pd bits in the status register are changed to indicate the event. see section 3.0 ?memory organization? and status register ( register 3-1 ) for more information. wdte<1:0> swdten device mode wdt mode 11 x xactive 10 x awake active sleep disabled 01 1 x active 0 disabled 00 x x disabled table 9-2: wdt clearing conditions conditions wdt wdte<1:0> = 00 cleared wdte<1:0> = 01 and swdten = 0 wdte<1:0> = 10 and enter sleep clrwdt command oscillator fail detected exit sleep + system clock = t1osc, extrc, intosc, extclk exit sleep + system clock = xt, hs, lp cleared until the end of ost change intosc divider (ircf bits) unaffected
? 2011 microchip technology inc. preliminary ds41569a-page 83 pic16lf1904/6/7 9.6 watchdog control register register 9-1: wdtcon: wat chdog timer control register u-0 u-0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 r/w-1/1 r/w-0/0 ? ? wdtps<4:0> swdten bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-1 wdtps<4:0>: watchdog timer period select bits (1) bit value = prescale rate 00000 = 1:32 (interval 1 ms nominal) 00001 = 1:64 (interval 2 ms nominal) 00010 = 1:128 (interval 4 ms nominal) 00011 = 1:256 (interval 8 ms nominal) 00100 = 1:512 (interval 16 ms nominal) 00101 = 1:1024 (interval 32 ms nominal) 00110 = 1:2048 (interval 64 ms nominal) 00111 = 1:4096 (interval 128 ms nominal) 01000 = 1:8192 (interval 256 ms nominal) 01001 = 1:16384 (interval 512 ms nominal) 01010 = 1:32768 (interval 1s nominal) 01011 = 1:65536 (interval 2s nominal) (reset value) 01100 = 1:131072 (2 17 ) (interval 4s nominal) 01101 = 1:262144 (2 18 ) (interval 8s nominal) 01110 = 1:524288 (2 19 ) (interval 16s nominal) 01111 = 1:1048576 (2 20 ) (interval 32s nominal) 10000 = 1:2097152 (2 21 ) (interval 64s nominal) 10001 = 1:4194304 (2 22 ) (interval 128s nominal) 10010 = 1:8388608 (2 23 ) (interval 256s nominal) 10011 = reserved. results in minimum interval (1:32) ? ? ? 11111 = reserved. results in minimum interval (1:32) bit 0 swdten: software enable/disable for watchdog timer bit if wdte<1:0> = 00 : this bit is ignored. if wdte<1:0> = 01 : 1 = wdt is turned on 0 = wdt is turned off if wdte<1:0> = 1x : this bit is ignored. note 1: times are approximate. wdt time is based on 31 khz lfintosc.
pic16lf1904/6/7 ds41569a-page 84 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 85 pic16lf1904/6/7 10.0 flash program memory control the flash program memory is readable and writable during normal operation over the full v dd range. program memory is indirectly addressed using special function registers (sfrs). the sfrs used to access program memory are: ?pmcon1 ?pmcon2 ?pmdatl ?pmdath ? pmadrl ?pmadrh when accessing the program memory, the pmdath:pmdatl register pair forms a 2-byte word that holds the 14-bit data for read/write, and the pmdath:pmdatl register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. the write time is controlled by an on-chip timer. the write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. the flash program memory can be protected in two ways; by code protection (cp bit in configuration word 1) and write protection (wrt<1:0> bits in configuration word 2). code protection (cp = 0 ) (1) , disables access, reading and writing, to the flash program memory via external device programmers. code protection does not affect the self-write and erase functionality. code protection can only be reset by a device programmer performing a bulk erase to the device, clearing all flash program memory, configuration bits and user ids. write protection prohibits self-write and erase to a portion or all of the flash program memory as defined by the bits wrt<1:0>. write protection does not affect a device programmers ability to read, write or erase the device. 10.1 pmadrl and pmadrh registers the pmadrh:pmadrl register pair can address up to a maximum of 32k words of program memory. when selecting a program address value, the msb of the address is written to the pmadrh register and the lsb is written to the pmadrl register. 10.1.1 pmcon1 and pmcon2 registers pmcon1 is the control register for flash program memory accesses. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set, in software. they are cleared by hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation to occur. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a reset during normal operation. in these situations, following reset, the user can check the wrerr bit and execute the appropriate error handling routine. the pmcon2 register is a write-only register. attempting to read the pmcon2 register will return all ? 0 ?s. to enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the pmcon2 register. the required unlock sequence prevents inadvertent writes to the program memory write latches and flash program memory. 10.2 flash program memory overview it is important to understand the flash program memory structure for erase and programming operations. flash program memory is arranged in rows. a row consists of a fixed number of 14-bit program memory words. a row is the minimum size that can be erased by user software. after a row has been erased, the user can reprogram all or a portion of this row. data to be written into the program memory row is written to 14-bit wide data write latches. these write latches are not directly accessible to the user, but may be loaded via sequential writes to the pmdath:pmdatl register pair. see table 10-1 for erase row size and the number of write latches for flash program memory. note 1: code protection of the entire flash program memory array is enabled by clearing the cp bit of configuration word 1. note: if the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in ram prior to the erase. then, new data and retained data can be written into the write latches to reprogram the row of flash program memory. how- ever, any unprogrammed locations can be written without first erasing the row. in this case, it is not necessary to save and rewrite the other previously programmed locations.
pic16lf1904/6/7 ds41569a-page 86 preliminary ? 2011 microchip technology inc. 10.2.1 reading the flash program memory to read a program memory location, the user must: 1. write the desired address to the pmadrh:pmadrl register pair. 2. clear the cfgs bit of the pmcon1 register. 3. then, set control bit rd of the pmcon1 register. once the read control bit is set, the program memory flash controller will use the second instruction cycle to read the data. this causes the second instruction immediately following the ? bsf pmcon1,rd ? instruction to be ignored. the data is available in the very next cycle, in the pmdath:pmdatl register pair; therefore, it can be read as two bytes in the following instructions. pmdath:pmdatl register pair will hold this value until another read or until it is written to by the user. figure 10-1: flash program memory read flowchart table 10-1: flash memory organization by device device row erase (words) write latches (words) pic16lf1904/6/7 32 32 note: the two instructions following a program memory read are required to be nop s. this prevents the user from executing a two-cycle instruction on the next instruction after the rd bit is set. start read operation select program or configuration memory (cfgs) select word address (pmadrh:pmadrl) end read operation instruction fetched ignored nop execution forced instruction fetched ignored nop execution forced initiate read operation (rd = 1 ) data read now in pmdath:pmdatl
? 2011 microchip technology inc. preliminary ds41569a-page 87 pic16lf1904/6/7 figure 10-2: flash program me mory read cycle execution example 10-1: flash program memory read q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pmcon1,rd executed here instr(pc + 1) executed here pc pc + 1 pmadrh,pmadrl pc+3 pc + 5 flash addr rd bit pmdath,pmdatl pc + 3 pc + 4 instr (pc + 1) instr(pc - 1) executed here instr(pc + 3) executed here instr(pc + 4) executed here flash data pmdath pmdatl register instr (pc) instr (pc + 3) instr (pc + 4) instruction ignored forced nop instr(pc + 2) executed here instruction ignored forced nop * this code block will read 1 word of program * memory at the memory address: prog_addr_hi : prog_addr_lo * data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select bank for pmcon registers movlw prog_addr_lo ; movwf pmadrl ; store lsb of address movlw prog_addr_hi ; movwl pmadrh ; store msb of address bcf pmcon1,cfgs ; do not select configuration space bsf pmcon1,rd ; initiate read nop ; ignored ( figure 10-1 ) nop ; ignored ( figure 10-1 ) movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location
pic16lf1904/6/7 ds41569a-page 88 preliminary ? 2011 microchip technology inc. 10.2.2 flash memory unlock sequence the unlock sequence is a mechanism that protects the flash program memory from unintended self-write pro- gramming or erasing. the sequence must be executed and completed without interruption to successfully complete any of the following operations: ?row erase ? load program memory write latches ? write of program memory write latches to pro- gram memory ? write of program memory write latches to user ids the unlock sequence consists of the following steps: 1. write 55h to pmcon2 2. write aah to pmcon2 3. set the wr bit in pmcon1 4. nop instruction 5. nop instruction once the wr bit is set, the processor will always force two nop instructions. when an erase row or program row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. when the operation is loading the program memory write latches, the processor will always force the two nop instructions and continue uninterrupted with the next instruction. since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. figure 10-3: flash program memory unlock sequence flowchart write 055h to pmcon2 start unlock sequence write 0aah to pmcon2 initiate write or erase operation (wr = 1 ) instruction fetched ignored nop execution forced end unlock sequence instruction fetched ignored nop execution forced
? 2011 microchip technology inc. preliminary ds41569a-page 89 pic16lf1904/6/7 10.2.3 erasing flash program memory while executing code, program memory can only be erased by rows. to erase a row: 1. load the pmadrh:pmadrl register pair with any address within the row to be erased. 2. clear the cfgs bit of the pmcon1 register. 3. set the free and wren bits of the pmcon1 register. 4. write 55h, then aah, to pmcon2 (flash programming unlock sequence). 5. set control bit wr of the pmcon1 register to begin the erase operation. see example 10-2 . after the ? bsf pmcon1,wr ? instruction, the processor requires two cycles to set up the erase operation. the user must place two nop instructions after the wr bit is set. the processor will halt internal operations for the typical 2 ms erase time. this is not sleep mode as the clocks and peripherals will continue to run. after the erase cycle, the processor will resume operation with the third instruction after the pmcon1 write instruction. figure 10-4: flash program memory erase flowchart disable interrupts (gie = 0 ) start erase operation select program or configuration memory (cfgs) select row address (pmadrh:pmadrl) select erase operation (free = 1 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end erase operation cpu stalls while erase operation completes (2 ms typical) figure 10-3
pic16lf1904/6/7 ds41569a-page 90 preliminary ? 2011 microchip technology inc. example 10-2: erasing one row of program memory ; this row erase routine assumes the following: ; 1. a valid address within the erase row is loaded in addrh:addrl ; 2. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrl movf addrl,w ; load lower 8 bits of erase address boundary movwf pmadrl movf addrh,w ; load upper 6 bits of erase address boundary movwf pmadrh bcf pmcon1,cfgs ; not configuration space bsf pmcon1,free ; specify an erase operation bsf pmcon1,wren ; enable writes movlw 55h ; start of required sequence to initiate erase movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin erase nop ; nop instructions are forced as processor starts nop ; row erase of program memory. ; ; the processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence
? 2011 microchip technology inc. preliminary ds41569a-page 91 pic16lf1904/6/7 10.2.4 writing to flash program memory program memory is programmed using the following steps: 1. load the address in pmadrh:pmadrl of the row to be programmed. 2. load each write latch with data. 3. initiate a programming operation. 4. repeat steps 1 through 3 until all data is written. before writing to program memory, the word(s) to be written must be erased or previously unwritten. pro- gram memory can only be erased one row at a time. no automatic erase occurs upon the initiation of the write. program memory can be written one or more words at a time. the maximum number of words written at one time is equal to the number of write latches. see figure 10-2 (row writes to program memory with 32 write latches) for more details. the write latches are aligned to the flash row address boundary defined by the upper 10-bits of pmadrh:pmadrl, (pmadrh<6:0>:pmadrl<7:5>) with the lower 5-bits of pmadrl, (pmadrl<4:0>) determining the write latch being loaded. write opera- tions do not cross these boundaries. at the completion of a program memory write operation, the data in the write latches is reset to contain 0x3fff. the following steps should be completed to load the write latches and program a row of program memory. these steps are divided into two parts. first, each write latch is loaded with data from the pmdath:pmdatl using the unlock sequence with lwlo = 1 . when the last word to be loaded into the write latch is ready, the lwlo bit is cleared and the unlock sequence executed. this initiates the programming operation, writing all the latches into flash program memory. 1. set the wren bit of the pmcon1 register. 2. clear the cfgs bit of the pmcon1 register. 3. set the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is ? 1 ?, the write sequence will only load the write latches and will not initiate the write to flash program memory. 4. load the pmadrh:pmadrl register pair with the address of the location to be written. 5. load the pmdath:pmdatl register pair with the program memory data to be written. 6. execute the unlock sequence ( section 10.2.2 ?flash memory unlock sequence? ). the write latch is now loaded. 7. increment the pmadrh:pmadrl register pair to point to the next location. 8. repeat steps 5 through 7 until all but the last write latch has been loaded. 9. clear the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is ? 0 ?, the write sequence will initiate the write to flash program memory. 10. load the pmdath:pmdatl register pair with the program memory data to be written. 11. execute the unlock sequence ( section 10.2.2 ?flash memory unlock sequence? ). the entire program memory latch content is now written to flash program memory. an example of the complete write sequence is shown in example 10-3 . the initial address is loaded into the pmadrh:pmadrl register pair; the data is loaded using indirect addressing. note: the special unlock sequence is required to load a write latch with data or initiate a flash programming operation. if the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. note: the program memory write latches are reset to the blank state (0x3fff) at the completion of every write or erase operation. as a result, it is not necessary to load all the program memory write latches. unloaded latches will remain in the blank state.
pic16lf1904/6/7 ds41569a-page 92 preliminary ? 2011 microchip technology inc. figure 10-5: block wr ites to flash program memory with 32 write latches pmdath pmdatl 7 5 0 7 0 6 8 14 14 14 write latch #31 1fh 14 14 pmadrh pmadrl 7 6 0 7 5 4 0 program memory write latches 14 14 14 5 10 pmadrh<6:0> :pmadrl<7:5> flash program memory row row address decode addr write latch #30 1eh write latch #1 01h write latch #0 00h addr addr addr 000h 001fh 001eh 0000h 0001h 001h 003fh 003eh 0020h 0021h 002h 005fh 005eh 0040h 0041h 3feh 7fdfh 7fdeh 7fc0h 7fc1h 3ffh 7fffh 7ffeh 7fe0h 7fe1h 14 r9 r8 r7 r6 r5 r4 r3 - r1 r0 c4 c3 c2 c1 c0 r2 pmadrl<4:0> 400h 8009h - 801fh 8000h - 8003h configuration words user id 0 - 3 8007h - 8008h 8006h deviceid revid reserved 8004h - 8005h reserved configuration memory cfgs = 0 cfgs = 1 - -
? 2011 microchip technology inc. preliminary ds41569a-page 93 pic16lf1904/6/7 figure 10-6: flash program memory write flowchart disable interrupts (gie = 0 ) start write operation select program or config. memory (cfgs) select row address (pmadrh:pmadrl) select write operation (free = 0 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end write operation no delay when writing to program memory latches determine number of words to be written into program or configuration memory. the number of words cannot exceed the number of words per row. (word_cnt) load the value to write (pmdath:pmdatl) update the word counter (word_cnt--) last word to write ? increment address (pmadrh:pmadrl++) unlock sequence (figure x-x) cpu stalls while write operation completes (2 ms typical) load write latches only (lwlo = 1 ) write latches to flash (lwlo = 0 ) no yes figure 10-3 figure 10-3
pic16lf1904/6/7 ds41569a-page 94 preliminary ? 2011 microchip technology inc. example 10-3: writing to flash program memory ; this write routine assumes the following: ; 1. 64 bytes of data are loaded, starting at the address in data_addr ; 2. each word of data to be written is made up of two adjacent bytes in data_addr, ; stored in little endian format ; 3. a valid starting address (the least significant bits = 00000) is loaded in addrh:addrl ; 4. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) ; bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrh ; bank 3 movf addrh,w ; load initial address movwf pmadrh ; movf addrl,w ; movwf pmadrl ; movlw low data_addr ; load initial data address movwf fsr0l ; movlw high data_addr ; load initial data address movwf fsr0h ; bcf pmcon1,cfgs ; not configuration space bsf pmcon1,wren ; enable writes bsf pmcon1,lwlo ; only load write latches loop moviw fsr0++ ; load first data byte into lower movwf pmdatl ; moviw fsr0++ ; load second data byte into upper movwf pmdath ; movf pmadrl,w ; check if lower bits of address are '00000' xorlw 0x1f ; check if we're on the last of 32 addresses andlw 0x1f ; btfsc status,z ; exit if last of 32 words, goto start_write ; movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor ; loads program memory write latches nop ; incf pmadrl,f ; still loading latches increment address goto loop ; write next latches start_write bcf pmcon1,lwlo ; no more loading latches - actually start flash program ; memory write movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor writes ; all the program memory write latches simultaneously nop ; to program memory. ; after nops, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence required sequence
? 2011 microchip technology inc. preliminary ds41569a-page 95 pic16lf1904/6/7 10.3 modifying flash program memory when modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a ram image. program memory is modified using the following steps: 1. load the starting address of the row to be modified. 2. read the existing data from the row into a ram image. 3. modify the ram image to contain the new data to be written into program memory. 4. load the starting address of the row to be rewritten. 5. erase the program memory row. 6. load the write latches with data from the ram image. 7. initiate a programming operation. figure 10-7: flash program memory modify flowchart start modify operation read operation (figure x.x) erase operation (figure x.x) modify image the words to be modified are changed in the ram image end modify operation write operation use ram image (figure x.x) an image of the entire row read must be stored in ram figure 10-1 figure 10-4 figure 10-5
pic16lf1904/6/7 ds41569a-page 96 preliminary ? 2011 microchip technology inc. 10.4 user id, device id and configuration word access instead of accessing program memory, the user id?s, device id/revision id and configuration words can be accessed when cfgs = 1 in the pmcon1 register. this is the region that would be pointed to by pc<15> = 1 , but not all addresses are accessible. different access may exist for reads and writes. refer to tab le 1 0- 2 . when read access is initiated on an address outside the parameters listed in tab le 1 0- 2 , the pmdath:pmdatl register pair is cleared, reading back ? 0 ?s. table 10-2: user id, device id and configuration word access (cfgs = 1 ) example 10-4: conf iguration word and device id access address function read access write access 8000h-8003h user ids yes yes 8006h device id/revision id yes no 8007h-8008h configuration words 1 and 2 yes no * this code block will read 1 word of program memory at the memory address: * prog_addr_lo (must be 00h-08h) data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select correct bank movlw prog_addr_lo ; movwf pmadrl ; store lsb of address clrf pmadrh ; clear msb of address bsf pmcon1,cfgs ; select configuration space bcf intcon,gie ; disable interrupts bsf pmcon1,rd ; initiate read nop ; executed (see figure 10-1 ) nop ; ignored (see figure 10-1 ) bsf intcon,gie ; restore interrupts movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location
? 2011 microchip technology inc. preliminary ds41569a-page 97 pic16lf1904/6/7 10.5 write verify it is considered good programming practice to verify that program memory writes agree with the intended value. since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in ram after the last write is complete. figure 10-8: flash program memory verify flowchart start verify operation read operation (figure x.x) end verify operation this routine assumes that the last row of data written was from an image saved in ram. this image will be used to verify the data currently stored in flash program memory. pmdat = ram image ? last word ? fail verify operation no yes yes no figure 10-1
pic16lf1904/6/7 ds41569a-page 98 preliminary ? 2011 microchip technology inc. 10.6 flash program memory control registers register 10-1: pmdatl: program memory data low byte register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u pmdat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 pmdat<7:0> : read/write value for least significant bits of program memory register 10-2: pmdath: program memory data high byte register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? pmdat<13:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 pmdat<13:8> : read/write value for most significant bits of program memory register 10-3: pmadrl: program me mory address low byte register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 pmadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 pmadr<7:0> : specifies the least significant bits for program memory address register 10-4: pmadrh: program memory address high byte register u-1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? pmadr<14:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 1 ? bit 6-0 pmadr<14:8> : specifies the most significant bits for program memory address
? 2011 microchip technology inc. preliminary ds41569a-page 99 pic16lf1904/6/7 register 10-5: pmcon1: progra m memory control 1 register u-1 (1) r/w-0/0 r/w-0/0 r/w/hc-0/0 r/w/hc-x/q (2) r/w-0/0 r/s/hc-0/0 r/s/hc-0/0 ? cfgs lwlo free wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cl eared hc = bit is cleared by hardware bit 7 unimplemented: read as ? 1 ? bit 6 cfgs: configuration select bit 1 = access configuration, user id and device id registers 0 = access flash program memory bit 5 lwlo: load write latches only bit (3) 1 = only the addressed program memory write latch is loaded/updated on the next wr command 0 = the addressed program memory write latch is loaded/ updated and a write of all program memory write latches will be initiated on the next wr command bit 4 free: program flash erase enable bit 1 = performs an erase operation on the next wr command (hardware cleared upon completion) 0 = performs a write operation on the next wr command bit 3 wrerr: program/erase error flag bit 1 = condition indicates an improper program or erase sequenc e attempt or termination (bit is set automatically on any set attempt (write ? 1 ?) of the wr bit). 0 = the program or erase operation completed normally. bit 2 wren: program/erase enable bit 1 = allows program/erase cycles 0 = inhibits programming/erasing of program flash bit 1 wr: write control bit 1 = initiates a program flash program/erase operation. the operation is self-timed and the bit is cl eared by hardware once operation is complete. the wr bit can only be set (not cleared) in software. 0 = program/erase operation to the flash is complete and inactive. bit 0 rd: read control bit 1 = initiates a program flash read. read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate a program flash read. note 1: unimplemented bit, read as ? 1 ?. 2: the wrerr bit is automatically set by hardware when a pr ogram memory write or erase operation is started (wr = 1 ) . 3: the lwlo bit is ignored during a progr am memory erase operation (free = 1 ).
pic16lf1904/6/7 ds41569a-page 100 preliminary ? 2011 microchip technology inc. table 10-3: summary of registers as sociated with flash program memory table 10-4: summary of configuration word with flash program memory register 10-6: pmcon2: progra m memory control 2 register w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 program memory control register 2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 flash memory unlock pattern bits to unlock writes, a 55h must be written first, followed by an aah, before setting the wr bit of the pmcon1 register. the value written to this register is used to unlock the writes. there are specific timing requirements on these writes. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page pmcon1 ? cfgs lwlo free wrerr wren wr rd 99 pmcon2 program memory control register 2 100 pmadrl pmadrl<7:0> 98 pmadrh ? pmadrh<6:0> 98 pmdatl pmdatl<7:0> 98 pmdath ? ? pmdath<5:0> 98 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the flash program memory module. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> ? 44 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> config2 13:8 ? ? lvp debug ? borv stvren pllen 45 7:0 ? ? ? vcapen (1) ? ?wrt<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the flash program memory.
? 2011 microchip technology inc. preliminary ds41569a-page 101 pic16lf1904/6/7 11.0 i/o ports in general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. however, the pin can still be read. each port has three standard registers for its operation. these registers are: ? trisx registers (data direction) ? portx registers (reads the levels on the pins of the device) ? latx registers (output latch) some ports may have one or more of the following additional registers. these registers are: ? anselx (analog select) ? wpux (weak pull-up) the data latch (lata register) is useful for read-modify-write operations on the value that the i/o pins are driving. a write operation to the lata register has the same affect as a write to the corresponding porta register. a read of the lata register reads of the values held in the i/o port latches, while a read of the porta register reads the actual i/o pin value. ports that support analog inputs have an associated anselx register. when an ansel bit is set, the digital input buffer associated with that bit is disabled. disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 11-1 . figure 11-1: generic i/o port operation example 11-1: initializing porta table 11-1: port availability per device device porta portb portc portd porte pic16lf1906 pic16lf1904/7 q d ck write latx data register i/o pin read portx write portx trisx read latx data bus to peripherals anselx v dd v ss ; this code example illustrates ; initializing the porta register. the ; other ports are initialized in the same ; manner. banksel porta ; clrf porta ;init porta banksel lata ;data latch clrf lata ; banksel ansela ; clrf ansela ;digital i/o banksel trisa ; movlw b'00111000' ;set ra<5:3> as inputs movwf trisa ;and set ra<2:0> as ;outputs
pic16lf1904/6/7 ds41569a-page 102 preliminary ? 2011 microchip technology inc. 11.1 porta registers porta is an 8-bit wide, bidirectional port. the corresponding data direction register is trisa ( register 11-2 ). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). the exception is ra3, which is input only and its tris bit will always read as ? 1 ?. example 11-1 shows how to initialize porta. reading the porta register ( register 11-1 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (lata). the trisa register ( register 11-2 ) controls the porta pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 11.1.1 ansela register the ansela register ( register 11-4 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansela bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the ansela bits has no effect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 11.1.2 porta functions and output priorities each porta pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 11-2 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc, comparator and capsense inputs, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown in table 11-2 . note: the ansela bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. table 11-2: porta output priority pin name function priority (1) ra0 seg12 (lcd) an0 ra0 ra1 seg7 an1 ra1 ra2 com2 an2 ra2 ra3 v ref + com3 seg15 an3 ra3 ra4 seg4 t0cki ra4 ra5 seg5 an4 ra5 ra6 clkout seg1 ra6 ra7 clkin seg2 ra7 note 1: priority listed from highest to lowest.
? 2011 microchip technology inc. preliminary ds41569a-page 103 pic16lf1904/6/7 register 11-1: porta: porta register r/w-x/x r/w-x/x r/w-x/x r/w-x/x r-x/x r/w-x/x r/w-x/x r/w-x/x ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ra<7:0> : porta i/o value bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to porta are actually written to the corresponding lata register. reads from the porta register is return of actual i/o pin values. register 11-2: trisa: porta tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 trisa<7:4>: porta tri-state control bits 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output bit 3 trisa3: ra3 port tri-state control bit this bit is always ? 1 ? as ra3 is an input only bit 2-0 trisa<2:0>: porta tri-state control bits 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output register 11-3: lata: porta data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 lata<7:0> : ra<7:4> output latch value bits (1) note 1: writes to porta are actually written to the corresponding lata register. reads from the porta register is return of actual i/o pin values.
pic16lf1904/6/7 ds41569a-page 104 preliminary ? 2011 microchip technology inc. table 11-3: summary of regist ers associated with porta table 11-4: summary of configuration word with porta register 11-4: ansela: porta analog select register u-0 u-0 r/w-1/1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? ansa5 ? ansa3 ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5 ansa5 : analog select between analog or digital function on pins ra5, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. bit 4 unimplemented: read as ? 0 ? bit 3-0 ansa<3:0> : analog select between analog or digital function on pins ra<3:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ?ansa5 ? ansa3 ansa2 ansa1 ansa0 104 lata lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 103 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 141 porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 103 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 103 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? ? ?clkouten boren<1:0> ? 44 7:0 cp mclre pwrte wdte<1:0> ? fosc<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by porta.
? 2011 microchip technology inc. preliminary ds41569a-page 105 pic16lf1904/6/7 11.2 portb registers portb is an 8-bit wide, bidirectional port. the corresponding data direction register is trisb ( register 11-6 ). setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 11-1 shows how to initialize an i/o port. reading the portb register ( register 11-5 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latb). the trisb register ( register 11-6 ) controls the portb pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisb register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 11.2.1 anselb register the anselb register ( register 11-8 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselb bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the anselb bits has no effect on digital out- put functions. a pin with tris clear and anselb set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when exe- cuting read-modify-write instructions on the affected port. 11.2.2 portb functions and output priorities each portb pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 11-5 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in table 11-5 . note: the anselb bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. table 11-5: portb output priority pin name function priority (1) rb0 seg0 an12 int ioc rb0 rb1 seg24 an10 vlcd1 ioc rb1 rb2 seg25 an8 vlcd2 ioc rb2 rb3 seg26 an9 vlcd3 ioc rb3 rb4 com0 an11 ioc rb4 rb5 com1 an13 ioc rb5 rb6 icdclk seg14 ioc rb6 rb7 icddat seg13 ioc rb7 note 1: priority listed from highest to lowest.
pic16lf1904/6/7 ds41569a-page 106 preliminary ? 2011 microchip technology inc. register 11-5: portb: portb register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 rb<7:0> : portb general purpose i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portb are actually written to the corresponding latb register. reads from the portb register is return of actual i/o pin values. register 11-6: trisb: portb tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 trisb<7:0>: portb tri-state control bits 1 = portb pin configured as an input (tri-stated) 0 = portb pin configured as an output register 11-7: latb: portb data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 latb<7:0> : portb output latch value bits (1) note 1: writes to portb are actually written to the corresponding latb register. reads from the portb register is return of actual i/o pin values.
? 2011 microchip technology inc. preliminary ds41569a-page 107 pic16lf1904/6/7 table 11-6: summary of regist ers associated with portb register 11-8: anselb: portb analog select register u-0 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ansb<5:0> : analog select between analog or digital function on pins rb<5:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. register 11-9: wpub: weak pull-up portb register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 wpub<7:0> : weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is autom atically disabled if the pin is in configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 107 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 106 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 106 trisb trisb7 trisb6 trisb5 tri sb4 trisb3 trisb2 trisb1 trisb0 106 wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 107 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by portb.
pic16lf1904/6/7 ds41569a-page 108 preliminary ? 2011 microchip technology inc. 11.3 portc registers portc is an 8-bit wide bidirectional port. the corresponding data direction register is trisc ( register 11-6 ). setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 11-1 shows how to initialize an i/o port. reading the portc register ( register 11-5 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latc). the trisc register ( register 11-6 ) controls the portc pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisc register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 11.3.1 portc functions and output priorities each portc pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 11-7 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in table 11-7 . table 11-7: portc output priority pin name function priority (1) rc0 t1oso t1cki rc0 rc1 t1osi rc1 rc2 seg2 rc2 rc3 seg6 rc3 rc4 seg11 t1g rc4 rc5 seg10 rc5 rc6 seg9 rc6 tx/ck rc7 seg8 rc7 rx/dt note 1: priority listed from highest to lowest.
? 2011 microchip technology inc. preliminary ds41569a-page 109 pic16lf1904/6/7 register 11-10: portc: portc register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 rc<7:0> : portc general purpose i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portc are actually written to the corresponding latc register. reads from the portc register is return of actual i/o pin values. register 11-11: trisc: portc tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 trisc<7:0>: portc tri-state control bits 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output register 11-12: latc: portc data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 latc<7:0> : portc output latch value bits (1) note 1: writes to portc are actually written to corresponding latc register. reads from portc register is return of actual i/o pin values.
pic16lf1904/6/7 ds41569a-page 110 preliminary ? 2011 microchip technology inc. table 11-8: summary of regist ers associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 106 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 106 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 106 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by portc.
? 2011 microchip technology inc. preliminary ds41569a-page 111 pic16lf1904/6/7 11.4 portd registers (pic16lf1904/7 only) portd is a 8-bit wide, bidirectional port. the corresponding data direction register is trisd ( register 11-14 ). setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 11-1 shows how to initialize an i/o port. reading the portd register ( register 11-13 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latd). the trisd register ( register 11-14 ) controls the portd pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisd register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 11.4.1 portd functions and output priorities each portd pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 11-9 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in table 11-9 . table 11-9: portd output priority pin name function priority (1) rd0 rd0 rd1 rd1 rd2 rd2 rd3 rd3 rd4 rd4 rd5 rd5 rd6 rd6 rd7 rd7 note 1: priority listed from highest to lowest.
pic16lf1904/6/7 ds41569a-page 112 preliminary ? 2011 microchip technology inc. register 11-13: portd: portd register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 rd<7:0> : portd general purpose i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portd are actually written to the corresponding latd register. reads from the portd register is return of actual i/o pin values. register 11-14: trisd: portd tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisd7 trisd6 trisd5 trisd4 trisd5 trisd5 trisd5 trisd4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 trisd<7:0>: portd tri-state control bits 1 = portd pin configured as an input (tri-stated) 0 = portd pin configured as an output register 11-15: latd: portb data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 latd<7:0> : portd output latch value bits (1) note 1: writes to portd are actually written to the corresponding latd register. reads from the portd register is return of actual i/o pin values.
? 2011 microchip technology inc. preliminary ds41569a-page 113 pic16lf1904/6/7 table 11-10: summary of regist ers associated with portd (1) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 112 portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 112 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 112 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by portd. note 1: pic16lf1904/7 only.
pic16lf1904/6/7 ds41569a-page 114 preliminary ? 2011 microchip technology inc. 11.5 porte registers re3 is input only, and also functions as mclr . the mclr feature can be disabled via a configuration fuse. re3 also supplies the programming voltage. the tris bit for re3 (trise3) always reads ? 1 ?. 11.5.1 porte functions and output priorities no output priorities, re3 is an input only pin. register 11-16: porte: porte register u-0 u-0 u-0 u-0 r-x/u u-0 u-0 u-0 ? ? ? ? re3 re2 (1) re1 (1) re0 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented : read as ? 0 ? bit 3-0 re<3:0> : porte input pin bit (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: re<2:0> are not implemented on the pic16lf1906. read as ? 0 ?. writes to re<2:0> are actually written to the corresponding late register. reads from the porte register is the return of actual i/o pin values. register 11-17: trise: porte tri-state register u-0 u-0 u-0 u-0 u-1 (1) u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented : read as ? 0 ? bit 3 unimplemented : read as ? 1 ? bit 2-0 unimplemented : read as ? 0 ? note 1: unimplemented, read as ? 1 ?.
? 2011 microchip technology inc. preliminary ds41569a-page 115 pic16lf1904/6/7 register 11-18: late: porte data latch register u-0 u-0 u-0 u-0 u-0 r/w-x/u r/w-x/u r/w-x/u ? ? ? ? ? late2 (2) late1 (2) late0 (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2-0 late<2:0> : porte output latch value bits (1) note 1: writes to porte are actually written to the corresponding late register. reads from the porte register is return of actual i/o pin values. 2: pic16lf1904/7 only. register 11-19: ansele: porte analog select register u-0 u-0 u-0 u-0 u-0 r/w-1/1 r/w-1/1 r/w-1/1 ? ? ? ? ?anse2 (2) anse1 (2) anse0 (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2-0 anse<2:0> : analog select between analog or digital function on pins re<2:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. 2: pic16lf1904/7 only.
pic16lf1904/6/7 ds41569a-page 116 preliminary ? 2011 microchip technology inc. table 11-11: summary of registers associated with porte register 11-20: wpue: weak pull-up porte register u-0 u-0 u-0 u-0 r/w-1/1 u-0 u-0 u-0 ? ? ? ? wpue3 ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3 wpue3: weak pull-up register bit 1 = pull-up enabled 0 = pull-up disabled bit 2-0 unimplemented: read as ? 0 ? note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon0 ? chs<4:0> go/done adon 131 ansele ? ? ? ? ?anse2 (2) anse1 (2) anse0 (2) 107 late ? ? ? ? ?late2 (2) late1 (2) late0 (2) 114 porte ? ? ? ?re3re2 (2) re1 (2) re0 (2) 114 trise ? ? ? ? ? (1) ? ? ? 114 wpue ? ? ? ?wpue3 ? ? ? 116 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porte. note 1: unimplemented, read as ? 1 ?. 2: pic16lf1904/7 only.
? 2011 microchip technology inc. preliminary ds41569a-page 117 pic16lf1904/6/7 12.0 interrupt-on-change the portb pins can be configured to operate as interrupt-on-change (ioc) pins. an interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. any individual portb pin, or combination of portb pins, can be configured to generate an interrupt. the interrupt-on-change module has the following features: ? interrupt-on-change enable (master switch) ? individual pin configuration ? rising and falling edge detection ? individual pin interrupt flags figure 12-1 is a block diagram of the ioc module. 12.1 enabling the module to allow individual portb pins to generate an interrupt, the iocie bit of the intcon register must be set. if the iocie bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 12.2 individual pin configuration for each portb pin, a rising edge detector and a falling edge detector are present. to enable a pin to detect a rising edge, the associated iocbpx bit of the iocbp register is set. to enable a pin to detect a falling edge, the associated iocbnx bit of the iocbn register is set. a pin can be configured to detect rising and falling edges simultaneously by setting both the iocbpx bit and the iocbnx bit of the iocbp and iocbn registers, respectively. 12.3 interrupt flags the iocbfx bits located in the iocbf register are status flags that correspond to the interrupt-on-change pins of portb. if an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the iocie bit is set. the iocif bit of the intcon register reflects the status of all iocbfx bits. 12.4 clearing interrupt flags the individual status flags, (iocbfx bits), can be cleared by resetting them to zero. if another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. in order to ensure that no detected edge is lost while clearing flags, only and operations masking out known changed bits should be performed. the following sequence is an example of what should be performed. example 12-1: 12.5 operation in sleep the interrupt-on-change interrupt sequence will wake the device from sleep mode, if the iocie bit is set. if an edge is detected while in sleep mode, the iocbf register will be updated prior to the first instruction executed out of sleep. figure 12-1: interrupt-on -change block diagram movlw 0xff xorwf iocbf, w andwf iocbf, f rbx from all other iocbfx individual pin detectors dq ck r dq ck r iocbnx iocbpx q2 clock cycle iocie ioc interrupt to cpu core iocbfx
pic16lf1904/6/7 ds41569a-page 118 preliminary ? 2011 microchip technology inc. 12.6 interrupt-on-change registers register 12-1: iocbp: interrupt-on- change positive edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 iocbp7 iocbp6 iocbp5 iocbp4 iocbp3 iocbp2 iocbp1 iocbp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 iocbp<7:0>: interrupt-on-change positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. associated status bit and interrupt flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 12-2: iocbn: interrupt-on-change negative edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 iocbn<7:0>: interrupt-on-change negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. associated status bit and interrupt flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 12-3: iocbf: interrupt-on-change flag register r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs - bit is set in hardware bit 7-0 iocbf<7:0>: interrupt-on-change flag bits 1 = an enabled change was detected on the associated pin. set when iocbpx = 1 and a rising edge was detected on rbx, or when iocbnx = 1 and a falling edge was detected on rbx. 0 = no change was detected, or the user cleared the detected change.
? 2011 microchip technology inc. preliminary ds41569a-page 119 pic16lf1904/6/7 table 12-1: summary of registers associated with interrupt-on-change name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 107 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 iocbf iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 118 iocbn iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 118 iocbp iocbp7 iocbp6 iocbp5 ioc bp4 iocbp3 iocbp2 iocbp1 iocbp0 118 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 106 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by interrupt-on-change.
pic16lf1904/6/7 ds41569a-page 120 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 121 pic16lf1904/6/7 13.0 fixed voltage reference (fvr) the fixed voltage reference (fvr) is a stable voltage reference, independent of v dd , with 1.024v or 2.048v selectable output levels. the output of the fvr can be configured to supply a reference voltage to the following: ? adc input channel ? adc positive reference the fvr can be enabled by setting the fvren bit of the fvrcon register. 13.1 independent gain amplifiers the output of the fvr supplied to the adc is routed through two independent programmable gain amplifiers. each amplifier can be configured to amplify the reference voltage by 1x or 2x, to produce the two possible voltage levels. the adfvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the adc module. refer- ence section 15.0 ?analog-to-digital converter (adc) module? for additional information. 13.2 fvr stabilization period when the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. once the circuits stabilize and are ready for use, the fvrrdy bit of the fvrcon register will be set. see section 22.0 ?electrical specifications? for the minimum delay requirement. figure 13-1: voltage reference block diagram fvr buffer1 (to adc module) x1 x2 + - 1.024v fixed reference fvren fvrrdy 2 adfvr<1:0> any peripheral requiring the fixed reference (see table 13-1 ) table 13-1: peripherals requiring the fixed voltage reference (fvr) peripheral conditions description hfintosc fosc<2:0> = 100 and ircf<3:0> = 000x intosc is active and device is not in sleep. bor boren<1:0> = 11 bor always enabled. boren<1:0> = 10 and borfs = 1 bor disabled in sleep mode, bor fast start enabled. boren<1:0> = 01 and borfs = 1 bor under software control, bor fast start enabled.
pic16lf1904/6/7 ds41569a-page 122 preliminary ? 2011 microchip technology inc. 13.3 fvr control registers table 13-2: summary of registers associated with fixed voltage reference register 13-1: fvrcon: fixed voltage reference control register r/w-0/0 r-q/q r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 fvren fvrrdy (1) tsen tsrng ? ?adfvr<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 fvren: fixed voltage reference enable bit 0 = fixed voltage reference is disabled 1 = fixed voltage reference is enabled bit 6 fvrrdy: fixed voltage reference ready flag bit (1) 0 = fixed voltage reference output is not ready or not enabled 1 = fixed voltage reference output is ready for use bit 5 tsen: temperature indicator enable bit 0 = temperature indicator is disabled 1 = temperature indicator is enabled bit 4 tsrng: temperature indicator range selection bit 0 =v out = v dd - 2v t (low range) 1 =v out = v dd - 4v t (high range) bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adfvr<1:0>: adc fixed voltage reference selection bit 00 = adc fixed voltage reference peripheral output is off. 01 = adc fixed voltage reference peripheral output is 1x (1.024v) 10 = adc fixed voltage reference peripheral output is 2x (2.048v) (2) 11 = reserved note 1: fvrrdy will output the true state of the band gap. 2: fixed voltage reference output cannot exceed v dd . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng ? ? adfvr1 adfvr0 122 legend: shaded cells are not used with the fixed voltage reference.
? 2011 microchip technology inc. preliminary ds41569a-page 123 pic16lf1904/6/7 14.0 temperature indicator module this family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. the circuit?s range of operating temperature falls between of -40c and +85c. the output is a voltage that is proportional to the device temperature. the output of the temperature indicator is internally connected to the device adc. the circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. a one- point calibration allows the circuit to indicate a temperature closely surrounding that point. a two-point calibration allows the circuit to sense the entire range of temperature more accurately. reference application note an1333, ? use and calibration of the internal temperature indicator ? (ds01333) for more details regarding the calibration process. 14.1 circuit operation figure 14-1 shows a simplified block diagram of the temperature circuit. the proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. equation 14-1 describes the output characteristics of the temperature indicator. equation 14-1: v out ranges the temperature sense circuit is integrated with the fixed voltage reference (fvr) module. see section 13.0 ?fixed voltage reference (fvr)? for more information. the circuit is enabled by setting the tsen bit of the fvrcon register. when disabled, the circuit draws no current. the circuit operates in either high or low range. the high range, selected by setting the tsrng bit of the fvrcon register, provides a wider output voltage. this provides more resolution over the temperature range, but may be less consistent from part to part. this range requires a higher bias voltage to operate and thus, a higher v dd is needed. the low range is selected by clearing the tsrng bit of the fvrcon register. the low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. the low range is provided for low voltage operation. figure 14-1: temperature circuit diagram 14.2 minimum operating v dd vs. minimum sensing temperature when the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. when the temperature circuit is operated in high range, the device operating voltage, v dd , must be high enough to ensure that the temperature circuit is cor- rectly biased. table 14-1 shows the recommended minimum v dd vs. range setting. table 14-1: recommended v dd vs. range 14.3 temperature output the output of the circuit is measured using the internal analog-to-digital converter. a channel is reserved for the temperature circuit output. refer to section 15.0 ?analog-to-digital converter (adc) module? for detailed information. 14.4 adc acquisition time to ensure accurate temperature measurements, the user must wait at least 200 ? s after the adc input multiplexer is connected to the temperature indicator output before the conversion is performed. in addition, the user must wait 200 ? s between sequential conversions of the temperature indicator output. high range: v out = v dd - 4v t low range: v out = v dd - 2v t min. v dd , tsrng = 1 min. v dd , tsrng = 0 3.6v 1.8v tsen adc mux tsrng v dd adc chs bits (adcon0 register) n v out
pic16lf1904/6/7 ds41569a-page 124 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 125 pic16lf1904/6/7 15.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the conversion result into the adc result registers (adresh:adresl register pair). figure 15-1 shows the block diagram of the adc. the adc voltage reference is software selectable to be either internally generated or externally supplied. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 15-1: adc block diagram reserved v dd v ref + adpref = 10 adpref = 00 fvr buffer1 note 1: when adon = 0 , all multiplexer inputs are disconnected. 2: see adcon0 register ( example 15-1 ) for detailed analog channel selection per device. adon (1) go/done v ss adc 00000 00001 00010 00011 00100 00101 00111 00110 01000 01001 01010 01011 01100 01101 11110 chs<4:0> (2) an0 an1 an2 an4 reserved reserved reserved v ref +/an3 an8 an9 an10 an11 an12 an13 11111 adresh adresl 10 16 adfm 0 = left justify 1 = right justify temperature indicator 11101
pic16lf1904/6/7 ds41569a-page 126 preliminary ? 2011 microchip technology inc. 15.1 adc configuration when configuring and using the adc the following functions must be considered: ? port configuration ? channel selection ? adc voltage reference selection ? adc conversion clock source ? interrupt control ? result formatting 15.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin should be configured for analog by setting the associated tris and ansel bits. refer to section 11.0 ?i/o ports? for more information. 15.1.2 channel selection there are up to 11 channel selections available: ? an<13:0> pins ? temperature indicator ? fvr (fixed voltage reference) output refer to section 13.0 ?fixed voltage reference (fvr)? and section 14.0 ?temperature indicator module? for more information on these channel selec- tions. the chs bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 15.2 ?adc operation? for more information. 15.1.3 adc voltage reference the adpref bits of the adcon1 register provides control of the positive voltage reference. the positive voltage reference can be: ?v ref + pin ?v dd ?fvr see section 13.0 ?fixed voltage reference (fvr)? for more details on the fixed voltage reference. 15.1.4 conversion clock the source of the conversion clock is software select- able via the adcs bits of the adcon1 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11.5 t ad peri- ods as shown in figure 15-2 . for correct conversion, the appropriate t ad specifica- tion must be met. refer to the a/d conversion require- ments in section 22.0 ?electrical specifications? for more information. table 15-1 gives examples of appro- priate adc clock selections. note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result.
? 2011 microchip technology inc. preliminary ds41569a-page 127 pic16lf1904/6/7 table 15-1: adc clock period (t ad ) v s . device operating frequencies figure 15-2: analog-to-dig ital conversion t ad cycles adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz f osc /2 000 100 ns (2) 125 ns (2) 250 ns (2) 500 ns (2) 2.0 ? s f osc /4 100 200 ns (2) 250 ns (2) 500 ns (2) 1.0 ? s4.0 ? s f osc /8 001 400 ns (2) 0.5 ? s (2) 1.0 ? s2.0 ? s 8.0 ? s (3) f osc /16 101 800 ns 1.0 ? s2.0 ? s4.0 ? s 16.0 ? s (3) f osc /32 010 1.6 ? s2.0 ? s4.0 ? s 8.0 ? s (3) 32.0 ? s (3) f osc /64 110 3.2 ? s4.0 ? s 8.0 ? s (3) 16.0 ? s (3) 64.0 ? s (3) f rc x11 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: the f rc source has a typical t ad time of 1.6 ? s for v dd . 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: the adc clock period (t ad ) and total adc conversion time can be minimized when the adc clock is derived from the system clock f osc . however, the f rc clock source must be used when conv ersions are to be performed with the device in sleep mode. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle:
pic16lf1904/6/7 ds41569a-page 128 preliminary ? 2011 microchip technology inc. 15.1.5 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruc- tion is always executed. if the user is attempting to wake-up from sleep and resume in-line code execu- tion, the gie and peie bits of the intcon register must be disabled. if the gie and peie bits of the intcon register are enabled, execution will switch to the interrupt service routine. 15.1.6 result formatting the 10-bit a/d conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the adcon1 register controls the output format. figure 15-3 shows the two output formats. figure 15-3: 10-bit a/d conv ersion result format note 1: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. 2: the adc operates during sleep only when the f rc oscillator is selected. adresh adresl (adfm = 0 )msb lsb bit 7 bit 0 bit 7 bit 0 10-bit a/d result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as ? 0 ? 10-bit a/d result
? 2011 microchip technology inc. preliminary ds41569a-page 129 pic16lf1904/6/7 15.2 adc operation 15.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a ? 1 ?. setting the go/done bit of the adcon0 register to a ? 1 ? will start the analog-to-digital conversion. 15.2.2 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif interrupt flag bit ? update the adresh and adresl registers with new conversion result 15.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adresh and adresl registers will be updated with the partially complete analog-to-digital conversion sample. incomplete bits will match the last bit converted. 15.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the f rc option. when the f rc clock source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than f rc , a sleep instruction causes the present conver- sion to be aborted and the adc module is turned off, although the adon bit remains set. note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 15.2.5 ?a/d conversion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated.
pic16lf1904/6/7 ds41569a-page 130 preliminary ? 2011 microchip technology inc. 15.2.5 a/d conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: ? disable pin output driver (refer to the tris register) ? configure pin as analog (refer to the ansel register) 2. configure the adc module: ? select adc conversion clock ? configure voltage reference ? select adc input channel ? turn on adc module 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result. 8. clear the adc interrupt flag (required if interrupt is enabled). example 15-1: a/d conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 15.3 ?a/d acquisition requirements? . ;this code block configures the adc ;for polling, vdd and vss references, frc ;clock and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b?11110000? ;right justify, frc ;clock movwf adcon1 ;vdd and vss vref banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansel ; bsf ansel,0 ;set ra0 to analog banksel adcon0 ; movlw b?00000001? ;select channel an0 movwf adcon0 ;turn adc on call sampletime ;acquisiton delay bsf adcon0,adgo ;start conversion btfsc adcon0,adgo ;is conversion done? goto $-1 ;no, test again banksel adresh ; movf adresh,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel adresl ; movf adresl,w ;read lower 8 bits movwf resultlo ;store in gpr space
? 2011 microchip technology inc. preliminary ds41569a-page 131 pic16lf1904/6/7 15.2.6 adc register definitions the following registers are used to control the operation of the adc. register 15-1: adcon0: a/ d control register 0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? chs<4:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-2 chs<4:0>: analog channel select bits 00000 =an0 00001 =an1 00010 =an2 00011 =an3 00100 =an4 00101 = reserved. no channel connected. 00110 = reserved. no channel connected. 00111 = reserved. no channel connected. 01000 =an8 01001 =an9 01010 =an10 01011 =an11 01100 =an12 01101 =an13 01110 = reserved. no channel connected. ? ? ? 11100 = reserved. no channel connected. 11101 = temperature indicator (2) 11110 = reserved. no channel connected. 11111 = fvr (fixed voltage reference) buffer 1 output (1) bit 1 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: see section 13.0 ?fixed voltage reference (fvr)? for more information. 2: see section 14.0 ?temperature indicator module? for more information.
pic16lf1904/6/7 ds41569a-page 132 preliminary ? 2011 microchip technology inc. register 15-2: adcon1: a/ d control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 adfm adcs<2:0> ? ? adpref<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 adfm: a/d result format select bit 1 = right justified. six most significant bits of adresh are set to ? 0 ? when the conversion result is loaded. 0 = left justified. six least significant bits of adresl are set to ? 0 ? when the conversion result is loaded. bit 6-4 adcs<2:0>: a/d conversion clock select bits 000 =f osc /2 001 =f osc /8 010 =f osc /32 011 =f rc (clock supplied from a dedicated rc oscillator) 100 =f osc /4 101 =f osc /16 110 =f osc /64 111 =f rc (clock supplied from a dedicated rc oscillator) bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adpref<1:0>: a/d positive voltage reference configuration bits 00 =v ref + is connected to v dd 01 = reserved 10 =v ref + is connected to external v ref + pin (1) 11 = reserved note 1: when selecting the fvr or the v ref + pin as the source of the positive reference, be aware that a minimum voltage specification exists. see section 22.0 ?electrical specifications? for details.
? 2011 microchip technology inc. preliminary ds41569a-page 133 pic16lf1904/6/7 register 15-3: adresh: adc result register high (adresh) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<9:2> : adc result register bits upper 8 bits of 10-bit conversion result register 15-4: adresl: adc result register low (adresl) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<1:0> ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 adres<1:0> : adc result register bits lower 2 bits of 10-bit conversion result bit 5-0 reserved : do not use.
pic16lf1904/6/7 ds41569a-page 134 preliminary ? 2011 microchip technology inc. register 15-5: adresh: adc result register high (adresh) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? ? ? ? ? adres<9:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 reserved : do not use. bit 1-0 adres<9:8> : adc result register bits upper 2 bits of 10-bit conversion result register 15-6: adresl: adc result register low (adresl) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<7:0> : adc result register bits lower 8 bits of 10-bit conversion result
? 2011 microchip technology inc. preliminary ds41569a-page 135 pic16lf1904/6/7 15.3 a/d acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 15-4 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), refer to figure 15-4 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an a/d acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 15-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 15-1: acquisition time example t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c ?? 0.05s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/511) ? = 10pf 1k ? 7k ? 10k ? ++ ?? ? ln(0.001957) = 1.12 = s v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? = v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k ? 5.0v v dd = assumptions: note: where n = number of bits of the adc. t acq 2s 1.12s 50c- 25c ?? 0.05 s/c ?? ?? ++ = 4.42s = note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification.
pic16lf1904/6/7 ds41569a-page 136 preliminary ? 2011 microchip technology inc. figure 15-4: analog input model figure 15-5: adc transfer function c pin va rs analog 5 pf v dd v t ? 0.6v v t ? 0.6v i leakage (1) r ic ? 1k sampling switch ss rss c hold = 10 pf v ss /v ref - 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss note 1: refer to section 22.0 ?electrical specifications? . r ss = resistance of sampling switch input pin 3ffh 3feh adc output code 3fdh 3fch 03h 02h 01h 00h full-scale 3fbh 0.5 lsb v ref - zero-scale transition v ref + transition 1.5 lsb full-scale range analog input voltage
? 2011 microchip technology inc. preliminary ds41569a-page 137 pic16lf1904/6/7 table 15-2: summary of registers associated with adc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon0 ? chs4 chs3 chs2 chs1 chs0 go/done adon 131 adcon1 adfm adcs2 adcs1 adcs0 ? ? adpref1 adpref0 132 adresh a/d result register high 133 , 134 adresl a/d result register low 133 , 134 ansela ? ?ansa5 ? ansa3 ansa2 ansa1 ansa0 104 anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 107 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie ? ? ? tmr1ie 73 pir1 tmr1gif adif rcif txif ? ? ? tmr1if 75 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 103 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 106 fvrcon fvren fvrrdy tsen tsrng ? ? adfvr1 adfvr0 122 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends on condition. shaded cells are not used for adc module.
pic16lf1904/6/7 ds41569a-page 138 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 139 pic16lf1904/6/7 16.0 timer0 module the timer0 module is an 8-bit timer/counter with the following features: ? 8-bit timer/counter register (tmr0) ? 8-bit prescaler (independent of watchdog timer) ? programmable internal or external clock source ? programmable external clock edge selection ? interrupt on overflow ? tmr0 can be used to gate timer1 figure 16-1 is a block diagram of the timer0 module. 16.1 timer0 operation the timer0 module can be used as either an 8-bit timer or an 8-bit counter. 16.1.1 8-bit timer mode the timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit timer mode is selected by clearing the tmr0cs bit of the option_reg register. when tmr0 is written, the increment is inhibited for two instruction cycles immediately following the write. 16.1.2 8-bit counter mode in 8-bit counter mode, the timer0 module will increment on every rising or falling edge of the t0cki pin. 8-bit counter mode using the t0cki pin is selected by setting the tmr0cs bit in the option_reg register to ? 1 ? . the rising or falling transition of the incrementing edge is determined by the tmr0se bit in the option_reg register. figure 16-1: block diagra m of the timer0 note: the value written to the tmr0 register can be adjusted, in order to account for the two instruction cycle delay when tmr0 is written. t0cki tmr0se tmr0 ps<2:0> data bus set flag bit tmr0if on overflow tmr0cs 0 1 0 1 8 8 8-bit prescaler f osc /4 psa sync 2 t cy overflow to timer1
pic16lf1904/6/7 ds41569a-page 140 preliminary ? 2011 microchip technology inc. 16.1.3 software programmable prescaler a software programmable prescaler is available for exclusive use with timer0. the prescaler is enabled by clearing the psa bit of the option_reg register. there are 8 prescaler options for the timer0 module ranging from 1:2 to 1:256. the prescale values are selectable via the ps<2:0> bits of the option_reg register. in order to have a 1:1 prescaler value for the timer0 module, the prescaler must be disabled by set- ting the psa bit of the option_reg register. the prescaler is not readable or writable. all instructions writing to the tmr0 register will clear the prescaler. 16.1.4 timer0 interrupt timer0 will generate an interrupt when the tmr0 register overflows from ffh to 00h. the tmr0if interrupt flag bit of the intcon register is set every time the tmr0 register overflows, regardless of whether or not the timer0 interrupt is enabled. the tmr0if bit can only be cleared in software. the timer0 interrupt enable is the tmr0ie bit of the intcon register. 16.1.5 8-bit counter mode synchronization when in 8-bit counter mode, the incrementing edge on the t0cki pin must be synchronized to the instruction clock. synchronization can be accomplished by sampling the prescaler output on the q2 and q4 cycles of the instruction clock. the high and low periods of the external clocking source must meet the timing requirements as shown in section 22.0 ?electrical specifications? . 16.1.6 operation during sleep timer0 cannot operate while the processor is in sleep mode. the contents of the tmr0 register will remain unchanged while the processor is in sleep mode. note: the watchdog timer (wdt) uses its own independent prescaler. note: the timer0 interrupt cannot wake the pro- cessor from sleep since the timer is fro- zen during sleep.
? 2011 microchip technology inc. preliminary ds41569a-page 141 pic16lf1904/6/7 table 16-1: summary of registers associated with timer0 register 16-1: option_reg: option register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpuen intedg tmr0cs tmr0se psa ps<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 wpuen : weak pull-up enable bit 1 = all weak pull-ups are disabled (except mclr , if it is enabled) 0 = weak pull-ups are enabled by individual wpux latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 tmr0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 tmr0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is not assigned to the timer0 module 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 bit value timer0 rate name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 141 tmr0 timer0 module register 139 * trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 103 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the timer0 module. * page provides register information.
pic16lf1904/6/7 ds41569a-page 142 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 143 pic16lf1904/6/7 17.0 timer1 module with gate control the timer1 module is a 16-bit timer/counter with the following features: ? 16-bit timer/counter register pair (tmr1h:tmr1l) ? programmable internal or external clock source ? 2-bit prescaler ? dedicated 32 khz oscillator circuit ? multiple timer1 gate (count enable) sources ? interrupt on overflow ? wake-up on overflow (external clock, asynchronous mode only) ? selectable gate source polarity ? gate toggle mode ? gate single-pulse mode ? gate value status ? gate event interrupt figure 17-1 is a block diagram of the timer1 module. figure 17-1: timer1 block diagram tmr1h tmr1l t1sync t1ckps<1:0> prescaler 1, 2, 4, 8 0 1 synchronized clock input 2 set flag bit tmr1if on overflow tmr1 (2) tmr1on note 1: st buffer is high speed type when using t1cki. 2: timer1 register increments on rising edge. 3: synchronize does not operate while in sleep. t1g t1osc f osc /4 internal clock t1oso t1osi t1oscen 1 0 t1cki tmr1cs<1:0> (1) synchronize (3) det sleep input tmr1ge 0 1 0 1 t1gpol d q ck q 0 1 t1gval t1gtm single pulse acq. control t1gspm t1ggo/done t1gss<1:0> en out 10 11 00 01 f osc internal clock r d en q q1 rd t1gcon data bus det interrupt tmr1gif set t1clk f osc /2 internal clock d en q t1g_in tmr1on reserved from timer0 overflow to lcd and clock switching modules
pic16lf1904/6/7 ds41569a-page 144 preliminary ? 2011 microchip technology inc. 17.1 timer1 operation the timer1 module is a 16-bit incrementing counter which is accessed through the tmr1h:tmr1l register pair. writes to tmr1h or tmr1l directly update the counter. when used with an internal clock source, the module is a timer and increments on every instruction cycle. when used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source. timer1 is enabled by configuring the tmr1on and tmr1ge bits in the t1con and t1gcon registers, respectively. table 17-1 displays the timer1 enable selections. 17.2 clock source selection the tmr1cs<1:0> and t1oscen bits of the t1con register are used to select the clock source for timer1. table 17-2 displays the clock source selections. 17.2.1 internal clock source when the internal clock source is selected, the tmr1h:tmr1l register pair will increment on multiples of f osc as determined by the timer1 prescaler. when the f osc internal clock source is selected, the timer1 register value will in crement by four counts every instruction clock cycle. due to this condition, a 2 lsb error in resolution will occur when reading the timer1 value. to utilize the full resolution of timer1, an asynchronous input signal must be used to gate the timer1 clock input. the following asynchronous source may be used: ? asynchronous event on the t1g pin to timer1 gate 17.2.2 external clock source when the external clock source is selected, the timer1 module may work as a timer or a counter. when enabled to count, timer1 is incremented on the rising edge of the external clock input t1cki or the capacitive sensing oscillator signal. either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. when used as a timer with a clock oscillator, an external 32.768 khz crystal can be used in conjunction with the dedicated internal oscillator circuit. table 17-1: timer1 enable selections tmr1on tmr1ge timer1 operation 00 off 01 off 10 always on 11 count enabled note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: ? timer1 enabled after por ? write to tmr1h or tmr1l ? timer1 is disabled ? timer1 is disabled (tmr1on = 0 ) when t1cki is high then timer1 is enabled (tmr1on = 1 ) when t1cki is low. table 17-2: clock source selections tmr1cs1 tmr1cs0 t1oscen clock source 00x instruction clock (f osc /4) 01x system clock (f osc ) 100 external clocking on t1cki pin 101 osc. circuit on t1osi/t1oso pins 11x lfintosc
? 2011 microchip technology inc. preliminary ds41569a-page 145 pic16lf1904/6/7 17.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the t1ckps bits of the t1con register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. 17.4 timer1 oscillator a dedicated low-power 32.768 khz oscillator circuit is built-in between pins t1osi (input) and t1oso. this internal circuit is to be used in conjunction with an external 32.768 khz crystal. the oscillator circuit is enabled by setting the t1oscen bit of the t1con register. the oscillator will continue to run during sleep. 17.5 timer1 operation in asynchronous counter mode if control bit t1sync of the t1con register is set, the external clock input is not synchronized. the timer increments asynchronously to the internal phase clocks. if the external clock source is selected then the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer (see section 17.5.1 ?reading and writing timer1 in asynchronous counter mode? ). 17.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the tmr1h:tmr1l register pair. 17.6 timer1 gate timer1 can be configured to count freely or the count can be enabled and disabled using timer1 gate circuitry. this is also referred to as timer1 gate enable. timer1 gate can also be driven by multiple selectable sources. 17.6.1 timer1 gate enable the timer1 gate enable mode is enabled by setting the tmr1ge bit of the t1gcon register. the polarity of the timer1 gate enable mode is configured using the t1gpol bit of the t1gcon register. when timer1 gate enable mode is enabled, timer1 will increment on the rising edge of the timer1 clock source. when timer1 gate enable mode is disabled, no incrementing will occur and timer1 will hold the current count. see figure 17-3 for timing details. note: the oscillator requires a start-up and stabilization time before use. thus, t1oscen should be set and a suitable delay observed prior to using timer1. a suitable delay similar to the ost delay can be implemented in software by clearing the tmr1if bit then presetting the tmr1h:tmr1l register pair to fc00h. the tmr1if flag will be set when 1024 clock cycles have elapsed, thereby indicating that the oscillator is running and reasonably stable. note: when switching from synchronous to asynchronous operation, it is possible to skip an increment. when switching from asynchronous to synchronous operation, it is possible to produce an additional increment. table 17-3: timer1 gate enable selections t1clk t1gpol t1g timer1 operation ? 00 counts ? 01 holds count ? 10 holds count ? 11 counts
pic16lf1904/6/7 ds41569a-page 146 preliminary ? 2011 microchip technology inc. 17.6.2 timer1 gate source selection the timer1 gate source can be selected from one of four different sources. source selection is controlled by the t1gss bits of the t1gcon register. the polarity for each available source is also selectable. polarity selection is controlled by the t1gpol bit of the t1gcon register. table 17-4: timer1 gate sources 17.6.2.1 t1g pin gate operation the t1g pin is one source for timer1 gate control. it can be used to supply an external source to the timer1 gate circuitry. 17.6.2.2 timer0 overflow gate operation when timer0 increments from ffh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the timer1 gate circuitry. 17.6.3 timer1 gate toggle mode when timer1 gate toggle mode is enabled, it is possi- ble to measure the full-cycle length of a timer1 gate signal, as opposed to the duration of a single level pulse. the timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the sig- nal. see figure 17-4 for timing details. timer1 gate toggle mode is enabled by setting the t1gtm bit of the t1gcon register. when the t1gtm bit is cleared, the flip-flop is cleared and held clear. this is necessary in order to control which edge is measured. 17.6.4 timer1 gate single-pulse mode when timer1 gate single-pulse mode is enabled, it is possible to capture a single pulse gate event. timer1 gate single-pulse mode is first enabled by setting the t1gspm bit in the t1gcon register. next, the t1ggo/done bit in the t1gcon register must be set. the timer1 will be fully enabled on the next incrementing edge. on the next trailing edge of the pulse, the t1ggo/done bit will automatically be cleared. no other gate events will be allowed to increment timer1 until the t1ggo/done bit is once again set in software. see figure 17-5 for timing details. if the single pulse gate mode is disabled by clearing the t1gspm bit in the t1gcon register, the t1ggo/done bit should also be cleared. enabling the toggle mode and the single-pulse mode simultaneously will permit both sections to work together. this allows the cycle times on the timer1 gate source to be measured. see figure 17-6 for timing details. 17.6.5 timer1 gate value status when timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. the value is stored in the t1gval bit in the t1gcon register. the t1gval bit is valid even when the timer1 gate is not enabled (tmr1ge bit is cleared). 17.6.6 timer1 gate event interrupt when timer1 gate event interrupt is enabled, it is pos- sible to generate an interrupt upon the completion of a gate event. when the falling edge of t1gval occurs, the tmr1gif flag bit in the pir1 register will be set. if the tmr1gie bit in the pie1 register is set, then an interrupt will be recognized. the tmr1gif flag bit operates even when the timer1 gate is not enabled (tmr1ge bit is cleared). t1gss timer1 gate source 00 timer1 gate pin 01 overflow of timer0 (tmr0 increments from ffh to 00h) note: enabling toggle mode at the same time as changing the gate polarity may result in indeterminate operation.
? 2011 microchip technology inc. preliminary ds41569a-page 147 pic16lf1904/6/7 17.7 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit of the pir1 register is set. to enable the interrupt on rollover, you must set these bits: ? tmr1on bit of the t1con register ? tmr1ie bit of the pie1 register ? peie bit of the intcon register ? gie bit of the intcon register the interrupt is cleared by clearing the tmr1if bit in the interrupt service routine. 17.8 timer1 operation during sleep timer1 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to set up the timer to wake the device: ? tmr1on bit of the t1con register must be set ? tmr1ie bit of the pie1 register must be set ? peie bit of the intcon register must be set ? t1sync bit of the t1con register must be set ? tmr1cs bits of the t1con register must be configured ? t1oscen bit of the t1con register must be configured the device will wake-up on an overflow and execute the next instructions. if the gie bit of the intcon register is set, the device will call the interrupt service routine. timer1 oscillator will continue to operate in sleep regardless of the t1sync bit setting. figure 17-2: timer1 incrementing edge note: the tmr1h:tmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. t1cki = 1 when tmr1 enabled t1cki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the count er prior to the first incrementing rising edge of the clock.
pic16lf1904/6/7 ds41569a-page 148 preliminary ? 2011 microchip technology inc. figure 17-3: timer1 gate enable mode figure 17-4: timer1 gate toggle mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 tmr1ge t1gpol t1gtm t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8
? 2011 microchip technology inc. preliminary ds41569a-page 149 pic16lf1904/6/7 figure 17-5: timer1 gate single-pulse mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif counting enabled on rising edge of t1g
pic16lf1904/6/7 ds41569a-page 150 preliminary ? 2011 microchip technology inc. figure 17-6: timer1 gate single-pulse and toggle combined mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 nn + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif t1gtm counting enabled on rising edge of t1g n + 4 n + 3
? 2011 microchip technology inc. preliminary ds41569a-page 151 pic16lf1904/6/7 17.9 timer1 control register the timer1 control register (t1con), shown in register 17-1 , is used to control timer1 and select the various features of the timer1 module. register 17-1: t1con: ti mer1 control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u u-0 r/w-0/u tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 tmr1cs<1:0>: timer1 clock source select bits 11 = reserved 10 = timer1 clock source is pin or oscillator: if t1oscen = 0 : external clock from t1cki pin (on the rising edge) if t1oscen = 1 : crystal oscillator on t1osi/t1oso pins 01 = timer1 clock source is system clock (f osc ) 00 = timer1 clock source is instruction clock (f osc /4) bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: lp oscillator enable control bit 1 = dedicated timer1 oscillator circuit enabled 0 = dedicated timer1 oscillator circuit disabled bit 2 t 1sync : timer1 external clock input synchronization control bit tmr1cs<1:0> = 1x 1 = do not synchronize external clock input 0 = synchronize external clock input with system clock (f osc ) tmr1cs<1:0> = 0x this bit is ignored. timer1 uses the internal clock when tmr1cs<1:0> = 1x . bit 1 unimplemented: read as ? 0 ? bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 clears timer1 gate flip-flop
pic16lf1904/6/7 ds41569a-page 152 preliminary ? 2011 microchip technology inc. 17.10 timer1 gate control register the timer1 gate control register (t1gcon), shown in register 17-2 , is used to control timer1 gate. register 17-2: t1gcon: timer1 gate control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w/hc-0/u r-x/x r/w-0/u r/w-0/u tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = bit is cleared by hardware bit 7 tmr1ge: timer1 gate enable bit if tmr1on = 0 : this bit is ignored if tmr1on = 1 : 1 = timer1 counting is controlled by the timer1 gate function 0 = timer1 counts regardless of timer1 gate function bit 6 t1gpol: timer1 gate polarity bit 1 = timer1 gate is active-high (timer1 counts when gate is high) 0 = timer1 gate is active-low (timer1 counts when gate is low) bit 5 t1gtm: timer1 gate toggle mode bit 1 = timer1 gate toggle mode is enabled 0 = timer1 gate toggle mode is disabled and toggle flip-flop is cleared timer1 gate flip-flop toggles on every rising edge. bit 4 t1gspm: timer1 gate single-pulse mode bit 1 = timer1 gate single-pulse mode is enabled and is controlling timer1 gate 0 = timer1 gate single-pulse mode is disabled bit 3 t1ggo/done : timer1 gate single-pulse acquisition status bit 1 = timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = timer1 gate single-pulse acquisition has completed or has not been started bit 2 t1gval: timer1 gate current state bit indicates the current state of the timer1 gate that could be provided to tmr1h:tmr1l. unaffected by timer1 gate enable (tmr1ge). bit 1-0 t1gss<1:0>: timer1 gate source select bits 00 = timer1 gate pin 01 = timer0 overflow output 10 = reserved 11 = reserved
? 2011 microchip technology inc. preliminary ds41569a-page 153 pic16lf1904/6/7 table 17-5: summary of registers associated with timer1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie ? ? ?tmr1ie 73 pir1 tmr1gif adif rcif txif ? ? ?tmr1if 75 tmr1h holding register for the most significant byte of the 16-bit tmr1 register 147 * tmr1l holding register for the least significant byte of the 16-bit tmr1 register 147 * trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 109 t1con tmr1cs1 tmr1cs0 t1ckps<1:0> t1oscen t1sync ?tmr1on 151 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss1 t1gss0 152 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the timer1 module. * page provides register information.
pic16lf1904/6/7 ds41569a-page 154 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 155 pic16lf1904/6/7 18.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) the enhanced universal synchronous asynchronous receiver transmitter (eusart) module is a serial i/o communications peripheral. it contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. the eusart, also known as a serial communications interface (sci), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. full-duplex mode is useful for communications with peripheral systems, such as crt terminals and personal computers. half-duplex synchronous mode is intended for communications with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms or other microcontrollers. these devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. the eusart module includes the following capabilities: ? full-duplex asynchronous transmit and receive ? two-character input buffer ? one-character output buffer ? programmable 8-bit or 9-bit character length ? address detection in 9-bit mode ? input buffer overrun error detection ? received character framing error detection ? half-duplex synchronous master ? half-duplex synchronous slave ? programmable clock and data polarity the eusart module implements the following additional features, making it ideally suited for use in local interconnect network (lin) bus systems: ? automatic detection and calibration of the baud rate ? wake-up on break reception ? 13-bit break character transmit block diagrams of the eusart transmitter and receiver are shown in figure 18-1 and figure 18-2 . figure 18-1: eusart transmi t block diagram txif txie interrupt txen tx9d msb lsb data bus txreg register transmit shift register (tsr) (8) 0 tx9 trmt tx/ck pin pin buffer and control 8 spbrgl spbrgh brg16 f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator ???
pic16lf1904/6/7 ds41569a-page 156 preliminary ? 2011 microchip technology inc. figure 18-2: eusart receiv e block diagram the operation of the eusart module is controlled through three registers: ? transmit status and control (txsta) ? receive status and control (rcsta) ? baud rate control (baudcon) these registers are detailed in register 18-1 , register 18-2 and register 18-3 , respectively. for all modes of eusart operation, the tris control bits corresponding to the rx/dt and tx/ck pins should be set to ? 1 ?. the eusart control will automatically reconfigure the pin from input to output, as needed. when the receiver or transmitter section is not enabled then the corresponding rx/dt or tx/ck pin may be used for general purpose input and output. rx/dt pin pin buffer and control data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? spbrgl spbrgh brg16 rcidl f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator
? 2011 microchip technology inc. preliminary ds41569a-page 157 pic16lf1904/6/7 18.1 eusart asynchronous mode the eusart transmits and receives data using the standard non-return-to-zero (nrz) format. nrz is implemented with two levels: a v oh mark state which represents a ? 1 ? data bit, and a v ol space state which represents a ? 0 ? data bit. nrz refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. an nrz transmission port idles in the mark state. each character transmission consists of one start bit followed by eight or nine data bits and is always terminated by one or more stop bits. the start bit is always a space and the stop bits are always marks. the most common data format is 8 bits. each transmitted bit persists for a period of 1/(baud rate). an on-chip dedicated 8-bit/16-bit baud rate generator is used to derive standard baud rate frequencies from the system oscillator. see table 18-5 for examples of baud rate configurations. the eusart transmits and receives the lsb first. the eusart?s transmitter and receiver are functionally independent, but share the same data format and baud rate. parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 18.1.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 18-1 . the heart of the transmitter is the serial transmit shift register (tsr), which is not directly accessible by software. the tsr obtains its data from the transmit buffer, which is the txreg register. 18.1.1.1 enabling the transmitter the eusart transmitter is enabled for asynchronous operations by configuring the following three control bits: ?txen = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the txen bit of the txsta register enables the transmitter circuitry of the eusart. clearing the sync bit of the txsta register configures the eusart for asynchronous operation. setting the spen bit of the rcsta register enables the eusart. the programmer must set the corresponding tris bit to configure the tx/ck i/o pin as an output. if the tx/ck pin is shared with an analog peripheral, the analog i/o function must be disabled by clearing the corresponding ansel bit. 18.1.1.2 transmitting data a transmission is initiated by writing a character to the txreg register. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txreg is immediately transferred to the tsr register. if the tsr still contains all or part of a previous character, the new character data is held in the txreg until the stop bit of the previous character has been transmitted. the pending character in the txreg is then transferred to the tsr in one t cy immediately following the stop bit transmission. the transmission of the start bit, data bits and stop bit sequence commences immediately following the transfer of the data to the tsr from the txreg. 18.1.1.3 transmit data polarity the polarity of the transmit data can be controlled with the cktxp bit of the baudcon register. the default state of this bit is ? 0 ? which selects high true transmit idle and data bits. setting the cktxp bit to ? 1 ? will invert the transmit data resulting in low true idle and data bits. the cktxp bit controls transmit data polarity only in asynchronous mode. in synchronous mode the cktxp bit has a different function. see section 18.4.1.2 ?clock polarity? . 18.1.1.4 transmit interrupt flag the txif interrupt flag bit of the pir1 register is set whenever the eusart transmitter is enabled and no character is being held for transmission in the txreg. in other words, the txif bit is only clear when the tsr is busy with a character and a new character has been queued for transmission in the txreg. the txif flag bit is not cleared immediately upon writing txreg. txif becomes valid in the second instruction cycle following the write execution. polling txif immediately following the txreg write will return invalid results. the txif bit is read-only, it cannot be set or cleared by software. the txif interrupt can be enabled by setting the txie interrupt enable bit of the pie1 register. however, the txif flag bit will be set whenever the txreg is empty, regardless of the state of the txie enable bit. to use interrupts when transmitting data, set the txie bit only when there is more data to send. clear the txie interrupt enable bit upon writing the last character of the transmission to the txreg. note: the txif transmitter interrupt flag is set when the txen enable bit is set.
pic16lf1904/6/7 ds41569a-page 158 preliminary ? 2011 microchip technology inc. 18.1.1.5 tsr status the trmt bit of the txsta register indicates the status of the tsr register. this is a read-only bit. the trmt bit is set when the tsr register is empty and is cleared when a character is transferred to the tsr register from the txreg. the trmt bit remains clear until all bits have been shifted out of the tsr register. no interrupt logic is tied to this bit, so the user needs to poll this bit to determine the tsr status. 18.1.1.6 transmitting 9-bit characters the eusart supports 9-bit character transmissions. when the tx9 bit of the txsta register is set, the eusart will shift 9 bits out for each character transmit- ted. the tx9d bit of the txsta register is the ninth, and most significant, data bit. when transmitting 9-bit data, the tx9d data bit must be written before writing the 8 least significant bits into the txreg. all nine bits of data will be transferred to the tsr shift register immediately after the txreg is written. a special 9-bit address mode is available for use with multiple receivers. see section 18.1.2.8 ?address detection? for more information on the address mode. 18.1.1.7 asynchronous transmission set-up: 1. initialize the spbrgh:spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 18.3 ?eusart baud rate generator (brg)? ). 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 4. if 9-bit transmission is desired, set the tx9 control bit. a set ninth data bit will indicate that the 8 least significant data bits are an address when the receiver is set for address detection. 5. set the cktxp control bit if inverted transmit data polarity is desired. 6. enable the transmission by setting the txen control bit. this will cause the txif interrupt bit to be set. 7. if interrupts are desired, set the txie interrupt enable bit. an interrupt will occur immediately provided that the gie and peie bits of the intcon register are also set. 8. if 9-bit transmission is selected, the ninth bit should be loaded into the tx9d data bit. 9. load 8-bit data into the txreg register. this will start the transmission. figure 18-3: asynchronous transmission note: the tsr register is not mapped in data memory, so it is not available to the user. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) tx/ck txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy pin
? 2011 microchip technology inc. preliminary ds41569a-page 159 pic16lf1904/6/7 figure 18-4: asynchronous transmiss ion (back-to-back) transmit shift reg write to txreg brg output (shift clock) tx/ck txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy pin table 18-1: registers associated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl ? sckp brg16 ? wue abden 166 baud2con abdovf rcidl ? sckp brg16 ? wue abden 166 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 93 pie1 tmr1gie adie rcie (1) txie (1) ? ? ? tmr1ie 94 pir1 tmr1gif adif rcif (1) txif (1) ? ? ? tmr1if 98 rcsta spen rx9 sren cren adden ferr oerr rx9d 165 spbrgl eusart baud rate generator, low byte 167 * spbrgh eusart baud rate generator, high byte 167 * txreg eusart transmit register 157 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 164 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for asynchronous transmission. * page provides register information. note 1: pic16lf1904/7 only.
pic16lf1904/6/7 ds41569a-page 160 preliminary ? 2011 microchip technology inc. 18.1.2 eusart asynchronous receiver the asynchronous mode would typically be used in rs-232 systems. the receiver block diagram is shown in figure 18-2 . the data is received on the rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial receive shift register (rsr) operates at the bit rate. when all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character first-in-first-out (fifo) memory. the fifo buffering allows reception of two complete characters and the start of a third character before software must start servicing the eusart receiver. the fifo and rsr registers are not directly accessible by software. access to the received data is via the rcreg register. 18.1.2.1 enabling the receiver the eusart receiver is enabled for asynchronous operation by configuring the following three control bits: ? cren = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the cren bit of the rcsta register enables the receiver circuitry of the eusart. clearing the sync bit of the txsta register configures the eusart for asynchronous operation. setting the spen bit of the rcsta register enables the eusart. the programmer must set the corresponding tris bit to configure the rx/dt i/o pin as an input. if the rx/dt pin is shared with an analog peripheral the analog i/o function must be disabled by clearing the corresponding ansel bit. 18.1.2.2 receiving data the receiver data recovery circuit initiates character reception on the falling edge of the first bit. the first bit, also known as the start bit, is always a zero. the data recovery circuit counts one-half bit time to the center of the start bit and verifies that the bit is still a zero. if it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the start bit. if the start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. the bit is then sampled by a majority detect circuit and the resulting ? 0 ? or ? 1 ? is shifted into the rsr. this repeats until all data bits have been sampled and shifted into the rsr. one final bit time is measured and the level sampled. this is the stop bit, which is always a ? 1 ?. if the data recovery circuit samples a ? 0 ? in the stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. see section 18.1.2.5 ?receive framing error? for more information on framing errors. immediately after all data bits and the stop bit have been received, the character in the rsr is transferred to the eusart receive fifo and the rcif interrupt flag bit of the pir1 register is set. the top character in the fifo is transferred out of the fifo by reading the rcreg register. 18.1.2.3 receive data polarity the polarity of the receive data can be controlled with the dtrxp bit of the baudcon register. the default state of this bit is ? 0 ? which selects high true receive idle and data bits. setting the dtrxp bit to ? 1 ? will invert the receive data resulting in low true idle and data bits. the dtrxp bit controls receive data polarity only in asynchronous mode. in synchronous mode the dtrxp bit has a different function. note 1: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. note: if the receive fifo is overrun, no additional characters will be received until the overrun condition is cleared. see section 18.1.2.6 ?receive overrun error? for more information on overrun errors.
? 2011 microchip technology inc. preliminary ds41569a-page 161 pic16lf1904/6/7 18.1.2.4 receive interrupts the rcif interrupt flag bit of the pir1 register is set whenever the eusart receiver is enabled and there is an unread character in the receive fifo. the rcif interrupt flag bit is read-only, it cannot be set or cleared by software. rcif interrupts are enabled by setting the following bits: ? rcie interrupt enable bit of the pie1 register ? peie peripheral interrupt enable bit of the intcon register ? gie global interrupt enable bit of the intcon register the rcif interrupt flag bit will be set when there is an unread character in the fifo, regardless of the state of interrupt enable bits. 18.1.2.5 receive framing error each character in the receive fifo buffer has a corresponding framing error status bit. a framing error indicates that a stop bit was not seen at the expected time. the framing error status is accessed via the ferr bit of the rcsta register. the ferr bit represents the status of the top unread character in the receive fifo. therefore, the ferr bit must be read before reading the rcreg. the ferr bit is read-only and only applies to the top unread character in the receive fifo. a framing error (ferr = 1 ) does not preclude reception of additional characters. it is not necessary to clear the ferr bit. reading the next character from the fifo buffer will advance the fifo to the next character and the next corresponding framing error. the ferr bit can be forced clear by clearing the spen bit of the rcsta register which resets the eusart. clearing the cren bit of the rcsta register does not affect the ferr bit. a framing error by itself does not generate an interrupt. 18.1.2.6 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before the fifo is accessed. when this happens the oerr bit of the rcsta register is set. the characters already in the fifo buffer can be read but no additional characters will be received until the error is cleared. the error must be cleared by either clearing the cren bit of the rcsta register or by resetting the eusart by clearing the spen bit of the rcsta register. 18.1.2.7 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcsta register is set, the eusart will shift 9 bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth and most significant data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the 8 least significant bits from the rcreg. 18.1.2.8 address detection a special address detection mode is available for use when multiple receivers share the same transmission line, such as in rs-485 systems. address detection is enabled by setting the adden bit of the rcsta register. address detection requires 9-bit character reception. when address detection is enabled, only characters with the ninth data bit set will be transferred to the receive fifo buffer, thereby setting the rcif interrupt bit. all other characters will be ignored. upon receiving an address character, user software determines if the address matches its own. upon address match, user software must disable address detection by clearing the adden bit before the next stop bit occurs. when user software detects the end of the message, determined by the message protocol used, software places the receiver back into the address detection mode by setting the adden bit. note: if all receive characters in the receive fifo have framing errors, repeated reads of the rcreg will not clear the ferr bit.
pic16lf1904/6/7 ds41569a-page 162 preliminary ? 2011 microchip technology inc. 18.1.2.9 asynchronous reception set-up: 1. initialize the spbrgh:spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 18.3 ?eusart baud rate generator (brg)? ). 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the serial port by setting the spen bit and the rx/dt pin tris bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie interrupt enable bit and set the gie and peie bits of the intcon register. 5. if 9-bit reception is desired, set the rx9 bit. 6. set the dtrxp if inverted receive polarity is desired. 7. enable reception by setting the cren bit. 8. the rcif interrupt flag bit will be set when a character is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 9. read the rcsta register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 10. get the received 8 least significant data bits from the receive buffer by reading the rcreg register. 11. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 18.1.2.10 9-bit address detection mode set-up this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 18.3 ?eusart baud rate generator (brg)? ). 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie interrupt enable bit and set the gie and peie bits of the intcon register. 5. enable 9-bit reception by setting the rx9 bit. 6. enable address detection by setting the adden bit. 7. set the dtrxp if inverted receive polarity is desired. 8. enable reception by setting the cren bit. 9. the rcif interrupt flag bit will be set when a character with the ninth bit set is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 10. read the rcsta register to get the error flags. the ninth data bit will always be set. 11. get the received 8 least significant data bits from the receive buffer by reading the rcreg register. software determines if this is the device?s address. 12. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 13. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and generate interrupts.
? 2011 microchip technology inc. preliminary ds41569a-page 163 pic16lf1904/6/7 figure 18-5: asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx/dt pin reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx/dt input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. rcidl table 18-2: registers associated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl ? sckp brg16 ? wue abden 166 baud2con abdovf rcidl ? sckp brg16 ? wue abden 166 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 93 pie1 tmr1gie adie rcie (1) txie (1) ? ? ? tmr1ie 94 pir1 tmr1gif adif rcif (1) txif (1) ? ? ? tmr1if 98 rcreg eusart receive register 160 * rcsta spen rx9 sren cren adden ferr oerr rx9d 165 spbrgl eusart baud rate generator, low byte 167 * spbrgh eusart baud rate generator, high byte 167 * trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 134 txsta csrc tx9 txen sync sendb brgh trmt tx9d 164 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for asynchronous reception. * page provides register information. note 1: pic16lf1904/7 only.
pic16lf1904/6/7 ds41569a-page 164 preliminary ? 2011 microchip technology inc. 18.2 clock accuracy with asynchronous operation the factory calibrates the internal oscillator block output (hfintosc). however, the hfintosc frequency may drift as v dd or temperature changes, and this directly affects the asynchronous baud rate. two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. the first (preferred) method uses the osctune register to adjust the hfintosc output. adjusting the value in the osctune register allows for fine resolution changes to the system clock source. see section 5.2 ?clock source types? for more information. the other method adjusts the value in the baud rate generator. this can be done automatically with the auto-baud detect feature (see section 18.3.1 ?auto-baud detect? ). there may not be fine enough resolution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency. register 18-1: txsta: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode : don?t care synchronous mode : 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode : 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode : don?t care bit 2 brgh: high baud rate select bit asynchronous mode : 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: ninth bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode.
? 2011 microchip technology inc. preliminary ds41569a-page 165 pic16lf1904/6/7 register 18-2: rcsta: receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care synchronous mode ? master : 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave don?t care bit 4 cren: continuous receive enable bit asynchronous mode : 1 = enables receiver 0 = disables receiver synchronous mode : 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enable interrupt and load the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 8-bit (rx9 = 0 ) : don?t care bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: ninth bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware.
pic16lf1904/6/7 ds41569a-page 166 preliminary ? 2011 microchip technology inc. register 18-3: baudcon: baud rate control register r-0/0 r-1/1 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 abdovf rcidl ? sckp brg16 ? wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 abdovf: auto-baud detect overflow bit asynchronous mode : 1 = auto-baud timer overflowed 0 = auto-baud timer did not overflow synchronous mode : don?t care bit 6 rcidl : receive idle flag bit asynchronous mode : 1 = receiver is idle 0 = start bit has been received and the receiver is receiving synchronous mode : don?t care bit 5 unimplemented: read as ? 0 ? bit 4 sckp : synchronous clock polarity select bit asynchronous mode : 1 = transmit inverted data to the tx/ck pin 0 = transmit non-inverted data to the tx/ck pin synchronous mode : 1 = data is clocked on rising edge of the clock 0 = data is clocked on falling edge of the clock bit 3 brg16: 16-bit baud rate generator bit 1 = 16-bit baud rate generator is used 0 = 8-bit baud rate generator is used bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode : 1 = receiver is waiting for a falling edge. no character will be received, byte rcif will be set. wue will automatically clear after rcif is set. 0 = receiver is operating normally synchronous mode : don?t care bit 0 abden : auto-baud detect enable bit asynchronous mode : 1 = auto-baud detect mode is enabled (clears when auto-baud is complete) 0 = auto-baud detect mode is disabled synchronous mode : don?t care
? 2011 microchip technology inc. preliminary ds41569a-page 167 pic16lf1904/6/7 18.3 eusart baud rate generator (brg) the baud rate generator (brg) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous eusart operation. by default, the brg operates in 8-bit mode. setting the brg16 bit of the baudcon register selects 16-bit mode. the spbrgh:spbrgl register pair determines the period of the free running baud rate timer. in asynchronous mode the multiplier of the baud rate period is determined by both the brgh bit of the txsta register and the brg16 bit of the baudcon register. in synchronous mode, the brgh bit is ignored. example 18-1 provides a sample calculation for deter- mining the desired baud rate, actual baud rate, and baud rate % error. typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in table 18-5 . it may be advantageous to use the high baud rate (brgh = 1 ), or the 16-bit brg (brg16 = 1 ) to reduce the baud rate error. the 16-bit brg mode is used to achieve slow baud rates for fast oscillator frequencies. writing a new value to the spbrgh, spbrgl register pair causes the brg timer to be reset (or cleared). this ensures that the brg does not wait for a timer overflow before outputting the new baud rate. if the system clock is changed during an active receive operation, a receive error or data loss may result. to avoid this problem, check the status of the rcidl bit to make sure that the receive operation is idle before changing the system clock. example 18-1: calculating baud rate error for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: solving for spbrgh:spbrgl: spbrgh: spbrgl f osc desired baud rate --------------------------------------------- 64 --------------------------------------------- 1 ? = desired baud rate f osc 64 [spbrgh:spbrg] 1 + ?? -------------------------------------------------------------------- - = 16000000 9600 ----------------------- - 64 ----------------------- -1 ? = 25.042 ?? 25 == actualbaudrate 16000000 64 25 1 + ?? -------------------------- - = 9615 = calc. baud rate desired baud rate ? desired baud rate -------------------------------------------------------------------------------------------- 9615 9600 ? ?? 9600 ---------------------------------- 0 . 1 6 % == baud rate % error = table 18-3: baud rate formulas configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n+1)] 001 8-bit/asynchronous f osc /[16 (n+1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n+1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrgh, spbrgl register pair
pic16lf1904/6/7 ds41569a-page 168 preliminary ? 2011 microchip technology inc. table 18-4: registers associated with baud rate generator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page baud1con abdovf rcidl ? sckp brg16 ? wue abden 166 baud2con abdovf rcidl ? sckp brg16 ? wue abden 166 rcsta spen rx9 sren cren adden ferr oerr rx9d 165 spbrgl eusart baud rate generator, low byte 167 * spbrgh eusart baud rate generator, high byte 167 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 164 legend: ? = unimplemented, read as ? 0 ?. shaded bits are not used by the brg. * page provides register information.
? 2011 microchip technology inc. preliminary ds41569a-page 169 pic16lf1904/6/7 table 18-5: baud rates for asynchronous modes baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300?? ? ?? ? ?? ? ?? ? 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k ? ? ? 57.60k 0.00 7? ? ? 57.60k 0.00 2 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ? ? ? 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 ? ? ? 9600 9615 0.16 12 ? ? ? 9600 0.00 5 ? ? ? 10417 10417 0.00 11 10417 0.00 5 ? ? ? ? ? ? 19.2k ? ? ? ? ? ? 19.20k 0.00 2 ? ? ? 57.6k ? ? ? ? ? ? 57.60k 0.00 0 ? ? ? 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ?? ? ?? ? ?? ? 1200 ? ? ? ? ? ? ? ? ? ? ? ? 2400 ? ? ? ? ? ? ? ? ? ?? ? 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5
pic16lf1904/6/7 ds41569a-page 170 preliminary ? 2011 microchip technology inc. baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ? ? ? ? ? ? 300 0.16 207 1200 ? ? ? 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? table 18-5: baud rates for asynchronous modes (continued)
? 2011 microchip technology inc. preliminary ds41569a-page 171 pic16lf1904/6/7 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 ? ? ? 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 ? ? ? table 18-5: baud rates for asynchronous modes (continued)
pic16lf1904/6/7 ds41569a-page 172 preliminary ? 2011 microchip technology inc. 18.3.1 auto-baud detect the eusart module supports automatic detection and calibration of the baud rate. in the auto-baud detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx signal, the rx signal is timing the brg. the baud rate generator is used to time the period of a received 55h (ascii ?u?) which is the sync character for the lin bus. the unique feature of this character is that it has five rising edges including the stop bit edge. setting the abden bit of the baudcon register starts the auto-baud calibration sequence ( figure 18.3.2 ). while the abd sequence takes place, the eusart state machine is held in idle. on the first rising edge of the receive line, after the start bit, the spbrgl begins counting up using the brg counter clock as shown in table 18-6 . the fifth rising edge will occur on the rx/dt pin at the end of the eighth bit period. at that time, an accumulated value totaling the proper brg period is left in the spbrgh:spbrgl register pair, the abden bit is automatically cleared, and the rcif interrupt flag is set. a read operation on the rcreg needs to be performed to clear the rcif interrupt. rcreg content should be discarded. when calibrating for modes that do not use the spbrgh register the user can verify that the spbrgl register did not overflow by checking for 00h in the spbrgh register. the brg auto-baud clock is determined by the brg16 and brgh bits as shown in table 18-6 . during abd, both the spbrgh and spbrgl registers are used as a 16-bit counter, independent of the brg16 bit setting. while calibrating the baud rate period, the spbrgh and spbrgl registers are clocked at 1/8th the brg base clock rate. the resulting byte measurement is the average bit time when clocked at full speed. figure 18-6: automatic baud rate calibration note 1: if the wue bit is set with the abden bit, auto-baud detection will occur on the byte following the break character (see section 18.3.3 ?auto-wake-up on break? ). 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible. 3: during the auto-baud process, the auto-baud counter starts counting at 1. upon completion of the auto-baud sequence, to achieve maximum accu- racy, subtract 1 from the spbrgh:spbrgl register pair. table 18-6: brg counter clock rates brg16 brgh brg base clock brg abd clock 00 f osc /64 f osc /512 01 f osc /16 f osc /128 10 f osc /16 f osc /128 11 f osc /4 f osc /32 note: during the abd sequence, spbrgl and spbrgh registers are both used as a 16-bit counter, independent of brg16 setting. brg value rx/dt pin abden bit rcif bit bit 0 bit 1 (interrupt) read rcreg brg clock start auto cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note 1: the abd sequence requires the eusart module to be configured in asynchronous mode. spbrgl xxh 1ch spbrgh xxh 00h rcidl
? 2011 microchip technology inc. preliminary ds41569a-page 173 pic16lf1904/6/7 18.3.2 auto-baud overflow during the course of automatic baud detection, the abdovf bit of the baudcon register will be set if the baud rate counter overflows before the fifth rising edge is detected on the rx pin. the abdovf bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the spbrgh:spbrgl register pair. after the abdovf has been set, the counter con- tinues to count until the fifth rising edge is detected on the rx/dt pin. upon detecting the fifth rx/dt edge, the hardware will set the rcif interrupt flag and clear the abden bit of the baudcon register. the rcif flag can be subsequently cleared by reading the rcreg. the abdovf flag can be cleared by software directly. to terminate the auto-baud process before the rcif flag is set, clear the abden bit then clear the abdovf bit. the abdovf bit will remain set if the abden bit is not cleared first. 18.3.3 auto-wake-up on break during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper character reception cannot be performed. the auto-wake-up feature allows the controller to wake-up due to activity on the rx/dt line. this feature is available only in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit of the baudcon register. once set, the normal receive sequence on rx/dt is disabled, and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rx/dt line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) the eusart module generates an rcif interrupt coincident with the wake-up event. the interrupt is generated synchronously to the q clocks in normal cpu operating modes ( figure 18-7 ), and asynchronously if the device is in sleep mode ( figure 18-8 ). the interrupt condition is cleared by reading the rcreg register. the wue bit is automatically cleared by the low-to-high transition on the rx line at the end of the break. this signals to the user that the break event is over. at this point, the eusart module is in idle mode waiting to receive the next character. 18.3.3.1 special considerations break character to avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. when the wake-up is enabled the function works independent of the low time on the data stream. if the wue bit is set and a valid non-zero character is received, the low time from the start bit to the first rising edge will be interpreted as the wake-up event. the remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. therefore, the initial character in the transmission must be all ? 0 ?s. this must be 10 or more bit times, 13-bit times recommended for lin bus, or any number of bit times for standard rs-232 devices. oscillator startup time oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., lp, xt or hs/pll mode). the sync break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. wue bit the wake-up event causes a receive interrupt by setting the rcif bit. the wue bit is cleared by hardware by a rising edge on rx/dt. the interrupt condition is then cleared by software by reading the rcreg register and discarding its contents. to ensure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process before setting the wue bit. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode.
pic16lf1904/6/7 ds41569a-page 174 preliminary ? 2011 microchip technology inc. figure 18-7: auto-wake-up bit (wue) timing during normal operation figure 18-8: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcreg note 1: the eusart remains in idle while the wue bit is set. q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcreg sleep command executed note 1 note 1: if the wake-up event requires long oscillator warm-up time, the automatic clearing of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart remains in idle while the wue bit is set. sleep ends
? 2011 microchip technology inc. preliminary ds41569a-page 175 pic16lf1904/6/7 18.3.4 break character sequence the eusart module has the capability of sending the special break character sequences that are required by the lin bus standard. a break character consists of a start bit, followed by 12 ? 0 ? bits and a stop bit. to send a break character, set the sendb and txen bits of the txsta register. the break character trans- mission is then initiated by a write to the txreg. the value of data written to txreg will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). the trmt bit of the txsta register indicates when the transmit operation is active or idle, just as it does during normal transmission. see figure 18-9 for the timing of the break character sequence. 18.3.4.1 break and sync transmit sequence the following sequence will start a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to enable the break sequence. 3. load the txreg with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txreg to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware and the sync character is then transmitted. when the txreg becomes empty, as indicated by the txif, the next data byte can be written to txreg. 18.3.5 receiving a break character the enhanced eusart module can receive a break character in two ways. the first method to detect a break character uses the ferr bit of the rcsta register and the received data as indicated by rcreg. the baud rate generator is assumed to have been initialized to the expected baud rate. a break character has been received when; ? rcif bit is set ? ferr bit is set ? rcreg = 00h the second method uses the auto-wake-up feature described in section 18.3.3 ?auto-wake-up on break? . by enabling this feature, the eusart will sample the next two transitions on rx/dt, cause an rcif interrupt, and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud detect feature. for both methods, the user can set the abden bit of the baudcon register before placing the eusart in sleep mode. figure 18-9: send break character sequence write to txreg dummy write brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txif bit (transmit interrupt flag) tx/ck (pin) trmt bit (transmit shift reg. empty flag) sendb (send break control bit) sendb sampled here auto cleared
pic16lf1904/6/7 ds41569a-page 176 preliminary ? 2011 microchip technology inc. 18.4 eusart synchronous mode synchronous serial communications are typically used in systems with a single master and one or more slaves. the master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. there are two signal lines in synchronous mode: a bidirectional data line and a clock line. slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. since the data line is bidirectional, synchronous operation is half-duplex only. half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. the eusart can operate as either a master or slave device. start and stop bits are not used in synchronous transmissions. 18.4.1 synchronous master mode the following bits are used to configure the eusart for synchronous master operation: ? sync = 1 ? csrc = 1 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. setting the csrc bit of the txsta register configures the device as a master. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the eusart. if the rx/dt or tx/ck pins are shared with an analog peripheral the analog i/o functions must be disabled by clearing the corresponding ansel bits. the tris bits corresponding to the rx/dt and tx/ck pins should be set. 18.4.1.1 master clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a master transmits the clock on the tx/ck line. the tx/ck pin output driver is automatically enabled when the eusart is configured for synchronous transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one clock cycle is generated for each data bit. only as many clock cycles are generated as there are data bits. 18.4.1.2 clock polarity a clock polarity option is provided for microwire compatibility. clock polarity is selected with the cktxp bit of the baudcon register. setting the cktxp bit sets the clock idle state as high. when the cktxp bit is set, the data changes on the falling edge of each clock and is sampled on the rising edge of each clock. clearing the cktxp bit sets the idle state as low. when the cktxp bit is cleared, the data changes on the rising edge of each clock and is sampled on the falling edge of each clock. 18.4.1.3 synchronous master transmission data is transferred out of the device on the rx/dt pin. the rx/dt and tx/ck pin output drivers are automat- ically enabled when the eusart is configured for synchronous master transmit operation. a transmission is initiated by writing a character to the txreg register. if the tsr still contains all or part of a previous character the new character data is held in the txreg until the last bit of the previous character has been transmitted. if this is the first character, or the pre- vious character has been completely flushed from the tsr, the data in the txreg is immediately transferred to the tsr. the transmission of the character com- mences immediately following the transfer of the data to the tsr from the txreg. each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. 18.4.1.4 data polarity the polarity of the transmit and receive data can be controlled with the dtrxp bit of the baudcon register. the default state of this bit is ? 0 ? which selects high true transmit and receive data. setting the dtrxp bit to ? 1 ? will invert the data resulting in low true transmit and receive data. note: the tsr register is not mapped in data memory, so it is not available to the user.
? 2011 microchip technology inc. preliminary ds41569a-page 177 pic16lf1904/6/7 18.4.1.5 synchronous master transmission set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 18.3 ?eusart baud rate generator (brg)? ). 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the synchronous master serial port by setting bits sync, spen and csrc. set the tris bits corresponding to the rx/dt and tx/ck i/o pins. 4. disable receive mode by clearing bits sren and cren. 5. enable transmit mode by setting the txen bit. 6. if 9-bit transmission is desired, set the tx9 bit. 7. if interrupts are desired, set the txie, gie and peie interrupt enable bits. 8. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 9. start transmission by loading data to the txreg register. figure 18-10: synchronous transmission figure 18-11: synchronous transmis sion (through txen) bit 0 bit 1 bit 7 word 1 bit 2 bit 0 bit 1 bit 7 rx/dt write to txreg reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrgl = 0 , continuous transmission of two 8-bit words. pin tx/ck pin tx/ck pin (sckp = 0 ) (sckp = 1 ) rx/dt pin tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit
pic16lf1904/6/7 ds41569a-page 178 preliminary ? 2011 microchip technology inc. table 18-7: registers associated wi th synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl ? sckp brg16 ? wue abden 166 baud2con abdovf rcidl ? sckp brg16 ? wue abden 166 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 93 pie1 tmr1gie adie rcie (1) txie (1) ? ? ? tmr1ie 94 pir1 tmr1gif adif rcif (1) txif (1) ? ? ? tmr1if 98 rcsta spen rx9 sren cren adden ferr oerr rx9d 165 spbrgl eusart baud rate generator, low byte 167 * spbrgh eusart baud rate generator, high byte 167 * trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 134 trisg ? ? ? trisg4 trisg3 trisg2 trisg1 trisg0 134 txreg eusart transmit register 157 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 164 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for synchronous master transmission. * page provides register information. note 1: pic16lf1904/7 only.
? 2011 microchip technology inc. preliminary ds41569a-page 179 pic16lf1904/6/7 18.4.1.6 synchronous master reception data is received at the rx/dt pin. the rx/dt pin output driver must be disabled by setting the corresponding tris bits when the eusart is configured for synchronous master receive operation. in synchronous mode, reception is enabled by setting either the single receive enable bit (sren of the rcsta register) or the continuous receive enable bit (cren of the rcsta register). when sren is set and cren is clear, only as many clock cycles are generated as there are data bits in a single character. the sren bit is automatically cleared at the completion of one character. when cren is set, clocks are continuously generated until cren is cleared. if cren is cleared in the middle of a character the ck clock stops immediately and the partial charac- ter is discarded. if sren and cren are both set, then sren is cleared at the completion of the first character and cren takes precedence. to initiate reception, set either sren or cren. data is sampled at the rx/dt pin on the trailing edge of the tx/ck clock pin and is shifted into the receive shift register (rsr). when a complete character is received into the rsr, the rcif bit is set and the character is automatically transferred to the two character receive fifo. the least significant eight bits of the top character in the receive fifo are available in rcreg. the rcif bit remains set as long as there are un-read characters in the receive fifo. 18.4.1.7 slave clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a slave receives the clock on the tx/ck line. the tx/ck pin output driver must be disabled by setting the associated tris bit when the device is configured for synchronous slave transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one data bit is transferred for each clock cycle. only as many clock cycles should be received as there are data bits. 18.4.1.8 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before rcreg is read to access the fifo. when this happens the oerr bit of the rcsta register is set. previous data in the fifo will not be overwritten. the two characters in the fifo buffer can be read, however, no additional characters will be received until the error is cleared. the oerr bit can only be cleared by clearing the overrun condition. if the overrun error occurred when the sren bit is set and cren is clear then the error is cleared by reading rcreg. if the overrun occurred when the cren bit is set then the error condition is cleared by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. 18.4.1.9 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcsta register is set the eusart will shift 9-bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth, and most significant, data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the 8 least significant bits from the rcreg. 18.4.1.10 synchronous master reception set-up: 1. initialize the spbrgh, spbrgl register pair for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the synchronous master serial port by setting bits sync, spen and csrc. disable rx/dt and tx/ck output drivers by setting the corresponding tris bits. 4. ensure bits cren and sren are clear. 5. if using interrupts, set the gie and peie bits of the intcon register and set rcie. 6. if 9-bit reception is desired, set bit rx9. 7. start reception by setting the sren bit or for continuous reception, set the cren bit. 8. interrupt flag bit rcif will be set when reception of a character is complete. an interrupt will be generated if the enable bit rcie was set. 9. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. read the 8-bit received data by reading the rcreg register. 11. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart.
pic16lf1904/6/7 ds41569a-page 180 preliminary ? 2011 microchip technology inc. figure 18-12: synchronous reception (master mode, sren) cren bit rx/dt write to bit sren sren bit rcif bit (interrupt) read rcreg ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . tx/ck pin tx/ck pin pin (sckp = 0 ) (sckp = 1 ) table 18-8: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl ? sckp brg16 ? wue abden 166 baud2con abdovf rcidl ? sckp brg16 ? wue abden 166 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 93 pie1 tmr1gie adie rcie (1) txie (1) ? ? ? tmr1ie 94 pir1 tmr1gif adif rcif (1) txif (1) ? ? ? tmr1if 98 rcreg eusart receive register 160 * rcsta spen rx9 sren cren adden ferr oerr rx9d 165 spbrgl eusart baud rate generator, low byte 167 * spbrgh eusart baud rate generator, high byte 167 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 164 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for synchronous master reception. * page provides register information. note 1: pic16lf1904/7 only.
? 2011 microchip technology inc. preliminary ds41569a-page 181 pic16lf1904/6/7 18.4.2 synchronous slave mode the following bits are used to configure the eusart for synchronous slave operation: ? sync = 1 ? csrc = 0 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. clearing the csrc bit of the txsta register configures the device as a slave. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the eusart. if the rx/dt or tx/ck pins are shared with an analog peripheral the analog i/o functions must be disabled by clearing the corresponding ansel bits. rx/dt and tx/ck pin output drivers must be disabled by setting the corresponding tris bits. 18.4.2.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical (see section 18.4.1.3 ?synchronous master transmission? ) , except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: 1. the first character will immediately transfer to the tsr register and transmit. 2. the second word will remain in txreg register. 3. the txif bit will not be set. 4. after the first character has been shifted out of tsr, the txreg register will transfer the second character to the tsr and the txif bit will now be set. 5. if the peie and txie bits are set, the interrupt will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will call the interrupt service routine. 18.4.2.2 synchronous slave transmission set-up: 1. set the sync and spen bits and clear the csrc bit. 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. clear the cren and sren bits. 4. if using interrupts, ensure that the gie and peie bits of the intcon register are set and set the txie bit. 5. if 9-bit transmission is desired, set the tx9 bit. 6. enable transmission by setting the txen bit. 7. if 9-bit transmission is selected, insert the most significant bit into the tx9d bit. 8. start transmission by writing the least significant 8 bits to the txreg register.
pic16lf1904/6/7 ds41569a-page 182 preliminary ? 2011 microchip technology inc. table 18-9: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl ? sckp brg16 ? wue abden 166 baud2con abdovf rcidl ? sckp brg16 ? wue abden 166 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 93 pie1 tmr1gie adie rcie (1) txie (1) ? ? ? tmr1ie 94 pir1 tmr1gif adif rcif (1) txif (1) ? ? ? tmr1if 98 rcsta spen rx9 sren cren adden ferr oerr rx9d 165 spbrgl eusart baud rate generator, low byte 167 * spbrgh eusart baud rate generator, high byte 167 * trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 134 txreg eusart transmit register 157 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 164 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for synchronous slave transmission. * page provides register information. note 1: pic16lf1904/7 only.
? 2011 microchip technology inc. preliminary ds41569a-page 183 pic16lf1904/6/7 18.4.2.3 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical ( section 18.4.1.6 ?synchronous master reception? ), with the following exceptions: ? sleep ? cren bit is always set, therefore the receiver is never idle ? sren bit, which is a ?don?t care? in slave mode a character may be received while in sleep mode by setting the cren bit prior to entering sleep. once the word is received, the rsr register will transfer the data to the rcreg register. if the rcie enable bit is set, the interrupt generated will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will branch to the interrupt vector. 18.4.2.4 synchronous slave reception set-up: 1. set the sync and spen bits and clear the csrc bit. 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. if using interrupts, ensure that the gie and peie bits of the intcon register are set and set the rcie bit. 4. if 9-bit reception is desired, set the rx9 bit. 5. set the cren bit to enable reception. 6. the rcif bit will be set when reception is complete. an interrupt will be generated if the rcie bit was set. 7. if 9-bit mode is enabled, retrieve the most significant bit from the rx9d bit of the rcsta register. 8. retrieve the 8 least significant bits from the receive fifo by reading the rcreg register. 9. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. table 18-10: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baud1con abdovf rcidl ? sckp brg16 ? wue abden 166 baud2con abdovf rcidl ? sckp brg16 ? wue abden 166 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 93 pie1 tmr1gie adie rcie txie ? ? ? tmr1ie 94 pir1 tmr1gif adif rcif txif ? ? ? tmr1if 98 rcreg eusart receive register 160 * rcsta spen rx9 sren cren adden ferr oerr rx9d 165 spbrgl eusart baud rate generator, low byte 167 * spbrgh eusart baud rate generator, high byte 167 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 164 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for synchronous slave reception. * page provides register information.
pic16lf1904/6/7 ds41569a-page 184 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 185 pic16lf1904/6/7 19.0 liquid crystal display (lcd) driver module the liquid crystal display (lcd) driver module generates the timing control to drive a static or multiplexed lcd panel. in the pic16lf1904/6/7 device, the module drives the panels of up to four commons and up to 116 total segments. the lcd module also provides control of the lcd pixel data. the lcd driver module supports: ? direct driving of lcd panel ? three lcd clock sources with selectable prescaler ? up to four common pins: - static (1 common) - 1/2 multiplex (2 commons) - 1/3 multiplex (3 commons) - 1/4 multiplex (4 commons) ? 19 segment pins (pic16lf1906 only) ? 29 segment pins (pic16lf1904/7 only) ? static, 1/2 or 1/3 lcd bias 19.1 lcd registers the module contains the following registers: ? lcd control register (lcdcon) ? lcd phase register (lcdps) ? lcd reference ladder register (lcdrl) ? lcd contrast control register (lcdcst) ? lcd reference voltage control register (lcdref) ? up to 4 lcd segment enable registers (lcdsen) ? up to 16 lcd data registers (lcddatan) figure 19-1: lcd driver module block diagram note: com3 and seg15 share the same physical pin on the pic16lf1906, therefore seg15 is not available when using 1/4 multiplex displays. data bus seg<28:0> (2) to i/o pads (1) lcddatax registers note 1: these are not directly connected to the i/o pads, but may be tri-stated, depending on the configuration of the lcd module. 2: com3 and seg15 share the same physical pin, therefore seg15 is not available when using 1/4 multi- plex displays. for the pic16lf1906 device only. com<3:0> clock source timing control select and prescaler lfintosc f osc /256 t1osc to i/o pads (1) lcdcon lcdps lcdsen mux
pic16lf1904/6/7 ds41569a-page 186 preliminary ? 2011 microchip technology inc. table 19-1: lcd segment and data registers the lcdcon register ( register 19-1 ) controls the operation of the lcd driver module. the lcdps regis- ter ( register 19-2 ) configures the lcd clock source prescaler and the type of waveform; type-a or type-b. the lcdsen registers ( register 19-5 ) configure the functions of the port pins. the following lcdsen registers are available: ? lcdse0 se<7:0> ? lcdse1 se<15:8> ? lcdse2 se<23:16> (pic16lf1904/1907 only) ? lcdse3 se<28:24> (1) (se<26:24> (2) ) once the module is initialized for the lcd panel, the individual bits of the lcddatan registers are cleared/set to represent a clear/dark pixel, respectively: ? lcddata0 seg<7:0>com0 ? lcddata1 seg<15:8>com0 ? lcddata2 seg<23:16>com0 ? lcddata3 seg<7:0>com1 ? lcddata4 seg<15:8>com1 ? lcddata5 seg<23:16>com1 ? lcddata6 seg<7:0>com2 ? lcddata7 seg<15:8>com2 ? lcddata8 seg<23:16>com2 ? lcddata9 seg<7:0>com3 ? lcddata10 seg<15:8>com3 ? lcddata11 seg<23:16>com3 (1) ? lcddata12 seg<28:24>com0 (1) (seg<26:24>) (2) ? lcddata15 seg<28:24>com1 (1) (seg<26:24>) (2) ? lcddata18 seg<28:24>com2 (1) (seg<26:24>) (2) ? lcddata21 seg<28:24>com3 (1) (seg<26:24>) (2) as an example, lcddatan is detailed in register 19-6 . once the module is configured, the lcden bit of the lcdcon register is used to enable or disable the lcd module. the lcd panel can also operate during sleep by clearing the slpen bit of the lcdcon register. device # of lcd registers segment enable data pic16lf1904/6/7 4 16 note 1: pic16lf1906 only.
? 2011 microchip technology inc. preliminary ds41569a-page 187 pic16lf1904/6/7 register 19-1: lcdcon: liquid crystal display (lcd) control register r/w-0/0 r/w-0/0 r/c-0/0 u-0 r/w-0/0 r/w-0/0 r/w-1/1 r/w-1/1 lcden slpen werr ? cs<1:0> lmux<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared c = only clearable bit bit 7 lcden: lcd driver enable bit 1 = lcd driver module is enabled 0 = lcd driver module is disabled bit 6 slpen: lcd driver enable in sleep mode bit 1 = lcd driver module is disabled in sleep mode 0 = lcd driver module is enabled in sleep mode bit 5 werr: lcd write failed error bit 1 = lcddatan register written while the wa bit of the lcdps register = 0 (must be cleared in software) 0 = no lcd write error bit 4 unimplemented: read as ? 0 ? bit 3-2 cs<1:0>: clock source select bits 00 = f osc /256 01 = t1osc (timer1) 1x = lfintosc (31 khz) bit 1-0 lmux<1:0>: commons select bits note 1: on these devices, com3 and seg15 are shared on one pin, limiting the device from driving 72 segments. lmux<1:0> multiplex maximum number of pixels bias pic16lf1906 pic16lf1904/7 00 static (com0) 19 29 static 01 1/2 (com<1:0>) 38 58 1/2 or 1/3 10 1/3 (com<2:0>) 57 87 1/2 or 1/3 11 1/4 (com<3:0>) 72 (1) 116 1/3
pic16lf1904/6/7 ds41569a-page 188 preliminary ? 2011 microchip technology inc. register 19-2: lcdps: lcd phase register r/w-0/0 r/w-0/0 r-0/0 r-0/0 r/w-0/0 r/w-0/0 r/w-1/1 r/w-1/1 wft biasmd lcda wa lp<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared c = only clearable bit bit 7 wft: waveform type bit 1 = type-b phase changes on each frame boundary 0 = type-a phase changes within each common type bit 6 biasmd: bias mode select bit when lmux<1:0> = 00 : 0 = static bias mode (do not set this bit to ? 1 ?) when lmux<1:0> = 01 : 1 = 1/2 bias mode 0 = 1/3 bias mode when lmux<1:0> = 10 : 1 = 1/2 bias mode 0 = 1/3 bias mode when lmux<1:0> = 11 : 0 = 1/3 bias mode (do not set this bit to ? 1 ?) bit 5 lcda: lcd active status bit 1 = lcd driver module is active 0 = lcd driver module is inactive bit 4 wa: lcd write allow status bit 1 = writing to the lcddatan registers is allowed 0 = writing to the lcddatan registers is not allowed bit 3-0 lp<3:0>: lcd prescaler selection bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1
? 2011 microchip technology inc. preliminary ds41569a-page 189 pic16lf1904/6/7 register 19-3: lcdref: lcd refe rence voltage control register r/w-0/0 u-0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 lcdire ? lcdiri ? vlcd3pe vlcd2pe vlcd1pe ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared c = only clearable bit bit 7 lcdire: lcd internal reference enable bit 1 = internal lcd reference is enabled and connected to the internal contrast control circuit 0 = internal lcd reference is disabled bit 6 unimplemented: read as ? 0 ? bit 5 lcdiri: lcd internal reference ladder idle enable bit allows the internal fvr buffer to shut down when the lcd reference ladder is in power mode ?b? 1 = when the lcd reference ladder is in power mode ?b?, the lcd internal fvr buffer is disabled. 0 = the lcd internal fvr buffer ignores the lcd reference ladder power mode. bit 4 unimplemented: read as ? 0 ? bit 3 vlcd3pe: vlcd3 pin enable bit 1 = the vlcd3 pin is connected to the internal bias voltage lcdbias3 (1) 0 = the vlcd3 pin is not connected bit 2 vlcd2pe: vlcd2 pin enable bit 1 = the vlcd2 pin is connected to the internal bias voltage lcdbias2 (1) 0 = the vlcd2 pin is not connected bit 1 vlcd1pe: vlcd1 pin enable bit 1 = the vlcd1 pin is connected to the internal bias voltage lcdbias1 (1) 0 = the vlcd1 pin is not connected bit 0 unimplemented: read as ? 0 ? note 1: normal pin controls of trisx and anselx are unaffected.
pic16lf1904/6/7 ds41569a-page 190 preliminary ? 2011 microchip technology inc. register 19-4: lcdcst: lcd contrast control register u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? ? ? lcdcst<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared c = only clearable bit bit 7-3 unimplemented: read as ? 0 ? bit 2-0 lcdcst<2:0>: lcd contrast control bits selects the resistance of the lcd contrast control resistor ladder bit value = resistor ladder 000 = minimum resistance (maximum contrast). resistor ladder is shorted. 001 = resistor ladder is at 1/7th of maximum resistance 010 = resistor ladder is at 2/7th of maximum resistance 011 = resistor ladder is at 3/7th of maximum resistance 100 = resistor ladder is at 4/7th of maximum resistance 101 = resistor ladder is at 5/7th of maximum resistance 110 = resistor ladder is at 6/7th of maximum resistance 111 = resistor ladder is at maximum resistance (minimum contrast).
? 2011 microchip technology inc. preliminary ds41569a-page 191 pic16lf1904/6/7 register 19-5: lcdsen: lcd segment enable registers r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 sen sen sen sen sen sen sen sen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 sen: segment enable bits 1 = segment function of the pin is enabled 0 = i/o function of the pin is enabled register 19-6: lcddatan: lcd data registers r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u segx-comy segx-comy segx-comy segx-comy segx-comy segx-comy segx-comy segx-comy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 segx-comy: pixel on bits 1 = pixel on (dark) 0 = pixel off (clear)
pic16lf1904/6/7 ds41569a-page 192 preliminary ? 2011 microchip technology inc. 19.2 lcd clock source selection the lcd module has 3 possible clock sources: ?f osc /256 ?t1osc ?lfintosc the first clock source is the system clock divided by 256 (f osc /256). this divider ratio is chosen to provide about 1 khz output when the system clock is 8 mhz. the divider is not programmable. instead, the lcd prescaler bits lp<3:0> of the lcdps register are used to set the lcd frame clock rate. the second clock source is the t1osc. this also gives about 1 khz when a 32.768 khz crystal is used with the timer1 oscillator. to use the timer1 oscillator as a clock source, the t1oscen bit of the t1con register should be set. the third clock source is the 31 khz lfintosc, which provides approximately 1 khz output. the second and third clock sources may be used to continue running the lcd while the processor is in sleep. using bits cs<1:0> of the lcdcon register can select any of these clock sources. 19.2.1 lcd prescaler a 4-bit counter is available as a prescaler for the lcd clock. the prescaler is not directly readable or writable; its value is set by the lp<3:0> bits of the lcdps register, which determine the prescaler assignment and prescale ratio. the prescale values are selectable from 1:1 through 1:16. figure 19-2: lcd cl ock generation cs<1:0> t1osc 32 khz crystal osc. lfintosc nominal = 31 khz static 1/2 1/3, 1/4 4 lmux<1:0> 4-bit prog 1, 2, 3, 4 ring counter com0 com1 com2 com3 256 f osc 2 32 lp<3:0> prescaler to ladder power control segment clock counter
? 2011 microchip technology inc. preliminary ds41569a-page 193 pic16lf1904/6/7 19.3 lcd bias voltage generation the lcd module can be configured for one of three bias types: ? static bias (2 voltage levels: v ss and v lcd ) ? 1/2 bias (3 voltage levels: v ss , 1/2 v lcd and v lcd ) ? 1/3 bias (4 voltage levels: v ss , 1/3 v lcd , 2/3 v lcd and v lcd ) table 19-2: lcd bias voltages so that the user is not forced to place external compo- nents and use up to three pins for bias voltage generation, internal contrast control and an internal reference ladder are provided internally to the pic16lf1904/6/7. both of these features may be used in conjunction with the exter- nal vlcd<3:1> pins, to provide maximum flexibility. refer to figure 19-3 . figure 19-3: lcd bias volt age generation block diagram static bias 1/2 bias 1/3 bias lcd bias 0 v ss v ss v ss lcd bias 1 ?1/2 v dd 1/3 v dd lcd bias 2 ?1/2 v dd 2/3 v dd lcd bias 3 v lcd 3v lcd 3v lcd 3 v dd lcdire vlcd3 lcdcst<2:0> vlcd3pe vlcd2 vlcd2pe vlcd1 vlcd1pe biasmd lcdbias3 lcdbias2 lcdbias1 lcdbias0 lcda lcda a b power mode switching (lrlap or lrlbp) 2 2 2
pic16lf1904/6/7 ds41569a-page 194 preliminary ? 2011 microchip technology inc. 19.4 lcd bias internal reference ladder the internal reference ladder can be used to divide the lcd bias voltage two or three equally spaced voltages that will be supplied to the lcd segment pins. to create this, the reference ladder consists of three matched resistors. refer to figure 19-3 . 19.4.1 bias mode interaction when in 1/2 bias mode (biasmd = 1 ), then the middle resistor of the ladder is shorted out so that only two voltages are generated. the current consumption of the ladder is higher in this mode, with the one resistor removed. table 19-3: lcd internal ladder power modes (1/3 bias) 19.4.2 power modes the internal reference ladder may be operated in one of three power modes. this allows the user to trade off lcd contrast for power in the specific application. the larger the lcd glass, the more capacitance is present on a physical lcd segment, requiring more current to maintain the same contrast level. three different power modes are available, lp, mp and hp. the internal reference ladder can also be turned off for applications that wish to provide an external ladder or to minimize power consumption. disabling the internal reference ladder results in all of the ladders being disconnected, allowing external voltages to be supplied. whenever the lcd module is inactive (lcda = 0 ), the internal reference ladder will be turned off. power mode nominal resistance of entire ladder nominal i dd low 3 mohm 1 a medium 300 kohm 10 a high 30 kohm 100 a
? 2011 microchip technology inc. preliminary ds41569a-page 195 pic16lf1904/6/7 19.4.3 automatic power mode switching as an lcd segment is electrically only a capacitor, cur- rent is drawn only during the interval where the voltage is switching. to minimize total device current, the lcd internal reference ladder can be operated in a different power mode for the transition portion of the duration. this is controlled by the lcdrl register ( register 19-7 ). the lcdrl register allows switching between two power modes, designated ?a? and ?b?. ?a? power mode is active for a programmable time, beginning at the time when the lcd segments transition. ?b? power mode is the remaining time before the segments or commons change again. the lrlat<2:0> bits select how long, if any, that the ?a? power mode is active. refer to figure 19-4 . to implement this, the 5-bit prescaler used to divide the 32 khz clock down to the lcd controller?s 1 khz base rate is used to select the power mode. figure 19-4: lcd internal reference l adder power mode switching diagram ? type a single segment time ?h00 ?h01 ?h02 ?h03 ?h04 ?h05 ?h06 ?h07 ?h0e ?h0f ?h00 ?h01 ?h3 power mode a power mode b mode a lrlat<2:0> 32 khz clock ladder power segment clock lrlat<2:0> segment data power mode com0 seg0 com0-seg0 control v 0 v 1 v 0 v 1 v 0 v 1 -v 1
pic16lf1904/6/7 ds41569a-page 196 preliminary ? 2011 microchip technology inc. figure 19-5: lcd internal reference ladder power mode switching diagram ? type a waveform (1/2 mux, 1/2 bias drive) single segment time ?h00 ?h01 ?h02 ?h03 ?h04 ?h05 ?h06 ?h07 ?h0f power mode a power mode b lrlat<2:0> = 011 32 khz clock ladder power segment clock segment data power mode com0-seg0 control v 1 v 2 v 0 -v 2 -v 1 single segment time ?h00 ?h01 ?h02 ?h03 ?h04 ?h05 ?h06 ?h07 ?h0f power mode a power mode b ?h0e ?h0e lrlat<2:0> = 011
? 2011 microchip technology inc. preliminary ds41569a-page 197 pic16lf1904/6/7 figure 19-6: lcd internal reference ladder power mode switching diagram ? type b waveform (1/2 mux, 1/2 bias drive) single segment time ?h00 ?h01 ?h02 ?h03 ?h0f power mode a power mode b 32 khz clock ladder power segment clock segment data power mode com0-seg0 control v 1 v 2 v 0 -v 2 -v 1 ?h0e single segment time ?h10 ?h11 ?h12 ?h13 ?h1f power mode a power mode b ?h1e single segment time ?h00 ?h01 ?h02 ?h03 ?h0f power mode a power mode b ?h0e single segment time ?h10 ?h11 ?h12 ?h13 ?h1f power mode a power mode b ?h1e lrlat<2:0> = 011 lrlat<2:0> = 011 lrlat<2:0> = 011 lrlat<2:0> = 011
pic16lf1904/6/7 ds41569a-page 198 preliminary ? 2011 microchip technology inc. register 19-7: lcdrl: lcd refere nce ladder control registers r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 lrlap<1:0> lrlbp<1:0> ? lrlat<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 lrlap<1:0>: lcd reference ladder a time power control bits during time interval a (refer to figure 19-4 ): 00 = internal lcd reference ladder is powered down and unconnected 01 = internal lcd reference ladder is powered in low-power mode 10 = internal lcd reference ladder is powered in medium-power mode 11 = internal lcd reference ladder is powered in high-power mode bit 5-4 lrlbp<1:0>: lcd reference ladder b time power control bits during time interval b (refer to figure 19-4 ): 00 = internal lcd reference ladder is powered down and unconnected 01 = internal lcd reference ladder is powered in low-power mode 10 = internal lcd reference ladder is powered in medium-power mode 11 = internal lcd reference ladder is powered in high-power mode bit 3 unimplemented: read as ? 0 ? bit 2-0 lrlat<2:0>: lcd reference ladder a time interval control bits sets the number of 32 khz clocks that the a time interval power mode is active for type a waveforms (wft = 0 ): 000 = internal lcd reference ladder is always in ?b? power mode 001 = internal lcd reference ladder is in ?a? power mode for 1 clock and ?b? power mode for 15 clocks 010 = internal lcd reference ladder is in ?a? power mode for 2 clocks and ?b? power mode for 14 clocks 011 = internal lcd reference ladder is in ?a? power mode for 3 clocks and ?b? power mode for 13 clocks 100 = internal lcd reference ladder is in ?a? power mode for 4 clocks and ?b? power mode for 12 clocks 101 = internal lcd reference ladder is in ?a? power mode for 5 clocks and ?b? power mode for 11 clocks 110 = internal lcd reference ladder is in ?a? power mode for 6 clocks and ?b? power mode for 10 clocks 111 = internal lcd reference ladder is in ?a? power mode for 7 clocks and ?b? power mode for 9 clocks for type b waveforms (wft = 1 ): 000 = internal lcd reference ladder is always in ?b? power mode. 001 = internal lcd reference ladder is in ?a? power mode for 1 clock and ?b? power mode for 31 clocks 010 = internal lcd reference ladder is in ?a? power mode for 2 clocks and ?b? power mode for 30 clocks 011 = internal lcd reference ladder is in ?a? power mode for 3 clocks and ?b? power mode for 29 clocks 100 = internal lcd reference ladder is in ?a? power mode for 4 clocks and ?b? power mode for 28 clocks 101 = internal lcd reference ladder is in ?a? power mode for 5 clocks and ?b? power mode for 27 clocks 110 = internal lcd reference ladder is in ?a? power mode for 6 clocks and ?b? power mode for 26 clocks 111 = internal lcd reference ladder is in ?a? power mode for 7 clocks and ?b? power mode for 25 clocks
? 2011 microchip technology inc. preliminary ds41569a-page 199 pic16lf1904/6/7 19.4.4 contrast control the lcd contrast control circuit consists of a seven-tap resistor ladder, controlled by the lcdcst bits. refer to figure 19-7 . the contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when lcdcst = 111 . whenever the lcd module is inactive (lcda = 0 ), the contrast control ladder will be turned off (open). figure 19-7: internal reference and contrast contro l block diagram 19.4.5 internal reference under firmware control, an internal reference for the lcd bias voltages can be enabled. when enabled, the source of this voltage can be either v ddio or a voltage 1 times the main fixed voltage reference (1.024v). when no internal reference is selected, the lcd con- trast control circuit is disabled and lcd bias must be provided externally. whenever the lcd module is inactive (lcda = 0 ), the internal reference will be turned off. when the internal reference is enabled and the fixed voltage reference is selected, the lcdiri bit can be used to minimize power consumption by tieing into the lcd reference ladder automatic power mode switching. when lcdiri = 1 and the lcd reference ladder is in power mode ?b?, the lcd internal fvr buffer is disabled. 19.4.6 vlcd<3:1> pins the vlcd<3:1> pins provide the ability for an external lcd bias network to be used instead of the internal lad- der. use of the vlcd<3:1> pins does not prevent use of the internal ladder. each vlcd pin has an indepen- dent control in the lcdref register ( register 19-3 ), allowing access to any or all of the lcd bias signals. this architecture allows for maximum flexibility in differ- ent applications for example, the vlcd<3:1> pins may be used to add capacitors to the internal reference ladder, increasing the drive capacity. for applications where the internal contrast control is insufficient, the firmware can choose to only enable the vlcd3 pin, allowing an external contrast control circuit to use the internal reference divider. lcdcst<2:0> analog rr rr 7 stages mux to top of reference ladder 7 0 3 3.072v v ddio from fvr buffer internal reference contrast control note: the lcd module automatically turns on the fixed voltage reference when needed.
pic16lf1904/6/7 ds41569a-page 200 preliminary ? 2011 microchip technology inc. 19.5 lcd multiplex types the lcd driver module can be configured into one of four multiplex types: ? static (only com0 is used) ? 1/2 multiplex (com<1:0> are used) ? 1/3 multiplex (com<2:0> are used) ? 1/4 multiplex (com<3:0> are used) the lmux<1:0> bit setting of the lcdcon register decides which of the lcd common pins are used (see table 19-4 for details). if the pin is a digital i/o, the corresponding tris bit controls the data direction. if the pin is a com drive, then the tris setting of that pin is overridden. table 19-4: common pin usage 19.6 segment enables the lcdsen registers are used to select the pin function for each segment pin. the selection allows each pin to operate as either an lcd segment driver or as one of the pin?s alternate functions. to configure the pin as a segment pin, the corresponding bits in the lcdsen registers must be set to ? 1 ?. if the pin is a digital i/o, the corresponding tris bit controls the data direction. any bit set in the lcdsen registers overrides any bit settings in the corresponding tris register. 19.7 pixel control the lcddatax registers contain bits which define the state of each pixel. each bit defines one unique pixel. register 19-6 shows the correlation of each bit in the lcddatax registers to the respective common and segment signals. any lcd pixel location not being used for display can be used as general purpose ram. 19.8 lcd frame frequency the rate at which the com and seg outputs change is called the lcd frame frequency. table 19-5: frame frequency formulas table 19-6: approximate frame frequency (in hz) using f osc @ 8 mhz, timer1 @ 32.768 khz or lfintosc multiplex lmux <1:0> com3 com2 com1 com1 static 00 unused unused unused active 1/2 01 unused unused active active 1/3 10 unused active active active 1/4 11 active active active active note: on a power-on reset, these pins are configured as normal i/o, not lcd pins. multiplex frame frequency (2) = static clock source (1) /(4 x (lcd prescaler) x 32 x 1)) 1/2 clock source (1) /(2 x (lcd prescaler) x 32 x 2)) 1/3 clock source (1) /(1 x (lcd prescaler) x 32 x 3)) 1/4 clock source (1) /(1 x (lcd prescaler) x 32 x 4)) note 1: clock source is f osc /256, t1osc or lfin- tosc. 2: see figure 19-2 . lp<3:0> static 1/2 1/3 1/4 2 122 122 162 122 3 81 81 108 81 461618161 549496549 641415441 735354735
? 2011 microchip technology inc. preliminary ds41569a-page 201 pic16lf1904/6/7 table 19-7: lcd segment mapping worksheet lcd function com0 com1 com2 com3 lcddatax address lcd segment lcddatax address lcd segment lcddatax address lcd segment lcddatax address lcd segment seg0 lcddata0, 0 lcddata3, 0 lcddata6, 0 lcddata9, 0 seg1 lcddata0, 1 lcddata3, 1 lcddata6, 1 lcddata9, 1 seg2 lcddata0, 2 lcddata3, 2 lcddata6, 2 lcddata9, 2 seg3 lcddata0, 3 lcddata3, 3 lcddata6, 3 lcddata9, 3 seg4 lcddata0, 4 lcddata3, 4 lcddata6, 4 lcddata9, 4 seg5 lcddata0, 5 lcddata3, 5 lcddata6, 5 lcddata9, 5 seg6 lcddata0, 6 lcddata3, 6 lcddata6, 6 lcddata9, 6 seg7 lcddata0, 7 lcddata3, 7 lcddata6, 7 lcddata9, 7 seg8 lcddata1, 0 lcddata4, 0 lcddata7, 0 lcddata10, 0 seg9 lcddata1, 1 lcddata4, 1 lcddata7, 1 lcddata10, 1 seg10 lcddata1, 2 lcddata4, 2 lcddata7, 2 lcddata10, 2 seg11 lcddata1, 3 lcddata4, 3 lcddata7, 3 lcddata10, 3 seg12 lcddata1, 4 lcddata4, 4 lcddata7, 4 lcddata10, 4 seg13 lcddata1, 5 lcddata4, 5 lcddata7, 5 lcddata10, 5 seg14 lcddata1, 6 lcddata4, 6 lcddata7, 6 lcddata10, 6 seg15 lcddata1, 7 lcddata4, 7 lcddata7, 7 lcddata10, 7 seg24 lcddata2, 5 lcddata5, 5 lcddata8, 5 lcddata11, 5 seg25 lcddata2, 6 lcddata5, 6 lcddata8, 6 lcddata11, 6 seg26 lcddata2, 7 lcddata5, 7 lcddata8, 7 lcddata11, 7 seg27 lcddata2, 3 lcddata5,3 lcddata8, 5 lcddata11, 5 seg28 lcddata2,4 lcddata5, 4 lcddata8, 5 lcddata11, 5
pic16lf1904/6/7 ds41569a-page 202 preliminary ? 2011 microchip technology inc. 19.9 lcd waveform generation lcd waveforms are generated so that the net ac voltage across the dark pixel should be maximized and the net ac voltage across the clear pixel should be minimized. the net dc voltage across any pixel should be zero. the com signal represents the time slice for each common, while the seg contains the pixel data. the pixel signal (com-seg) will have no dc component and it can take only one of the two rms values. the higher rms value will create a dark pixel and a lower rms value will create a clear pixel. as the number of commons increases, the delta between the two rms values decreases. the delta represents the maximum contrast that the display can have. the lcds can be driven by two types of waveform: type-a and type-b. in type-a waveform, the phase changes within each common type, whereas in type-b waveform, the phase changes on each frame boundary. thus, type-a waveform maintains 0 v dc over a single frame, whereas type-b waveform takes two frames. figure 19-8 through figure 19-18 provide waveforms for static, half-multiplex, 1/3-multiplex and 1/4-multiplex drives for type-a and type-b waveforms. figure 19-8: type-a/type-b waveforms in static drive note 1: if sleep has to be executed with lcd sleep disabled (lcdcon is ? 1 ?), then care must be taken to execute sleep only when v dc on all the pixels is ? 0 ?. 2: when the lcd clock source is f osc /256, if sleep is executed, irrespective of the lcdcon setting, the lcd immediately goes into sleep. thus, take care to see that v dc on all pixels is ? 0 ? when sleep is executed. v 1 v 0 com0 pin seg0 pin com0-seg0 com0-seg1 seg1 pin v 1 v 0 v 1 v 0 v 0 v 1 -v 1 v 0 1 frame com0 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 segment voltage (active) segment voltage (inactive)
? 2011 microchip technology inc. preliminary ds41569a-page 203 pic16lf1904/6/7 figure 19-9: type-a waveforms in 1/2 mux, 1/2 bias drive v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 -v 2 -v 1 v 2 v 1 v 0 -v 2 -v 1 com0 pin com1 pin seg0 pin seg1 pin com0-seg0 com0-seg1 1 frame com1 com0 seg0 seg1 seg2 seg3 1 segment time note: 1 frame = 2 single segment times. segment voltage segment voltage (active) (inactive)
pic16lf1904/6/7 ds41569a-page 204 preliminary ? 2011 microchip technology inc. figure 19-10: type-b waveforms in 1/2 mux, 1/2 bias drive v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 -v 2 -v 1 v 2 v 1 v 0 -v 2 -v 1 com0 pin com1 pin seg0 pin seg1 pin com0-seg0 com0-seg1 com1 com0 seg2 seg3 2 frames note: 1 frame = 2 single segment times. 1 segment time segment voltage (active) segment voltage (inactive) seg0 seg1
? 2011 microchip technology inc. preliminary ds41569a-page 205 pic16lf1904/6/7 figure 19-11: type-a waveforms in 1/2 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 pin com1 pin seg0 pin seg1 pin com0-seg0 com0-seg1 1 frame com1 com0 seg2 seg3 segment voltage (active) segment voltage (inactive) seg0 seg1 1 segment time note: 1 frame = 2 single segment times.
pic16lf1904/6/7 ds41569a-page 206 preliminary ? 2011 microchip technology inc. figure 19-12: type-b waveforms in 1/2 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 pin com1 pin seg0 pin seg1 pin com0-seg0 com0-seg1 com1 com0 seg2 seg3 segment voltage (active) segment voltage (inactive) seg0 seg1 2 frames note: 1 frame = 2 single segment times. 1 segment time
? 2011 microchip technology inc. preliminary ds41569a-page 207 pic16lf1904/6/7 figure 19-13: type-a waveforms in 1/3 mux, 1/2 bias drive v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 -v 2 -v 1 v 2 v 1 v 0 -v 2 -v 1 com0 pin com1 pin com2 pin seg0 and seg1 pin com0-seg0 com0-seg1 com2 com1 com0 seg0 seg1 seg2 seg2 pins segment voltage (inactive) segment voltage (active) 1 frame 1 segment time note: 1 frame = 2 single segment times.
pic16lf1904/6/7 ds41569a-page 208 preliminary ? 2011 microchip technology inc. figure 19-14: type-b waveforms in 1/3 mux, 1/2 bias drive v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 v 2 v 1 v 0 -v 2 -v 1 v 2 v 1 v 0 -v 2 -v 1 com0 pin com1 pin com2 pin seg0 pin seg1 pin com0-seg0 com0-seg1 com2 com1 com0 seg0 seg1 seg2 segment voltage (inactive) segment voltage (active) 2 frames note: 1 frame = 2 single segment times. 1 segment time
? 2011 microchip technology inc. preliminary ds41569a-page 209 pic16lf1904/6/7 figure 19-15: type-a waveforms in 1/3 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 pin com1 pin com2 pin seg0 and seg1 pin com0-seg0 com0-seg1 com2 com1 com0 seg0 seg1 seg2 seg2 pins segment voltage (inactive) segment voltage (active) 1 frame 1 segment time note: 1 frame = 2 single segment times.
pic16lf1904/6/7 ds41569a-page 210 preliminary ? 2011 microchip technology inc. figure 19-16: type-b waveforms in 1/3 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 pin com1 pin com2 pin seg0 pin seg1 pin com0-seg0 com0-seg1 com2 com1 com0 seg0 seg1 seg2 segment voltage (inactive) segment voltage (active) 2 frames note: 1 frame = 2 single segment times. 1 segment time
? 2011 microchip technology inc. preliminary ds41569a-page 211 pic16lf1904/6/7 figure 19-17: type-a waveforms in 1/4 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 pin com1 pin com2 pin com3 pin seg0 pin seg1 pin com0-seg0 com0-seg1 com3 com2 com1 com0 seg0 seg1 segment voltage (active) segment voltage (inactive) 1 frame 1 segment time note: 1 frame = 2 single segment times.
pic16lf1904/6/7 ds41569a-page 212 preliminary ? 2011 microchip technology inc. figure 19-18: type-b waveforms in 1/4 mux, 1/3 bias drive v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 v 3 v 2 v 1 v 0 -v 3 -v 2 -v 1 com0 pin com1 pin com2 pin com3 pin seg0 pin seg1 pin com0-seg0 com0-seg1 com2 com1 com0 seg0 seg1 com3 segment voltage (active) segment voltage (inactive) 2 frames note: 1 frame = 2 single segment times. 1 segment time
? 2011 microchip technology inc. preliminary ds41569a-page 213 pic16lf1904/6/7 19.10 lcd interrupts the lcd module provides an interrupt in two cases. an interrupt when the lcd controller goes from active to inactive controller. an interrupt also provides unframe boundaries for type b waveform. the lcd timing gen- eration provides an interrupt that defines the lcd frame timing. 19.10.1 lcd interrupt on module shutdown an lcd interrupt is generated when the module com- pletes shutting down (lcda goes from ? 1 ? to ? 0 ?). 19.10.2 lcd frame interrupts a new frame is defined to begin at the leading edge of the com0 common signal. the interrupt will be set immediately after the lcd controller completes access- ing all pixel data required for a frame. this will occur at a fixed interval before the frame boundary (t fint ), as shown in figure 19-19 . the lcd controller will begin to access data for the next frame within the interval from the interrupt to when the controller begins to access data after the interrupt (t fwr ). new data must be writ- ten within t fwr , as this is when the lcd controller will begin to access the data for the next frame. when the lcd driver is running with type-b waveforms and the lmux<1:0> bits are not equal to ? 00 ? (static drive), there are some additional issues that must be addressed. since the dc voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames. if the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a dc component would be introduced into the panel. therefore, when using type-b waveforms, the user must synchronize the lcd pixel updates to occur within a subframe after the frame interrupt. to correctly sequence writing while in type-b, the interrupt will only occur on complete phase intervals. if the user attempts to write when the write is disabled, the werr bit of the lcdcon register is set and the write does not occur. note: the lcd frame interrupt is not generated when the type-a waveform is selected and when the type-b with no multiplex (static) is selected.
pic16lf1904/6/7 ds41569a-page 214 preliminary ? 2011 microchip technology inc. figure 19-19: waveforms and interrupt ti ming in quarter- duty cycle drive (example ? type-b, non-static) frame boundary frame boundary lcd interrupt occurs controller accesses next frame data t fint t fwr t fwr =t frame /2*(lmux<1:0> + 1) + t cy /2 t fint =(t fwr /2 ? (2 t cy + 40 ns)) ? minimum = 1.5(t frame /4) ? (2 t cy + 40 ns) (t fwr /2 ? (1 t cy + 40 ns)) ? maximum = 1.5(t frame /4) ? (1 t cy + 40 ns) frame boundary v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 com0 com1 com2 com3 2 frames
? 2011 microchip technology inc. preliminary ds41569a-page 215 pic16lf1904/6/7 19.11 operation during sleep the lcd module can operate during sleep. the selection is controlled by bit slpen of the lcdcon register. setting the slpen bit allows the lcd module to go to sleep. clearing the slpen bit allows the module to continue to operate during sleep. if a sleep instruction is executed and slpen = 1 , the lcd module will cease all functions and go into a very low-current consumption mode. the module will stop operation immediately and drive the minimum lcd voltage on both segment and common lines. figure 19-20 shows this operation. the lcd module can be configured to operate during sleep. the selection is controlled by bit slpen of the lcdcon register. clearing slpen and correctly con- figuring the lcd module clock will allow the lcd mod- ule to operate during sleep. setting slpen and correctly executing the lcd module shutdown will dis- able the lcd module during sleep and save power. if a sleep instruction is executed and slpen = 1 , the lcd module will immediately cease all functions, drive the outputs to vss and go into a very low-current mode. the sleep instruction should only be executed after the lcd module has been disabled and the current cycle completed, thus ensuring that there are no dc voltages on the glass. to disable the lcd module, clear the lcden bit. the lcd module will complete the disabling process after the current frame, clear the lcda bit and optionally cause an interrupt. the steps required to properly enter sleep with the lcd disabled are: ? clear lcden ? wait for lcda = 0 either by polling or by interrupt ? execute sleep if slpen = 0 and sleep is executed while the lcd module clock source is f osc /4, then the lcd module will halt with the pin driving the last lcd voltage pat- tern. prolonged exposure to a fixed lcd voltage pat- tern will cause damage to the lcd glass. to prevent lcd glass damage, either perform the proper lcd module shutdown prior to sleep, or change the lcd module clock to allow the lcd module to continue operation during sleep. if a sleep instruction is executed and slpen = 0 and the lcd module clock is either t1osc or lfintosc, the module will continue to display the current contents of the lcddata registers. while in sleep, the lcd data cannot be changed. if the lcdie bit is set, the device will wake from sleep on the next lcd frame boundary. the lcd module current consumption will not decrease in this mode; however, the overall device power consumption will be lower due to the shutdown of the cpu and other peripherals. table 19-8 shows the status of the lcd module during a sleep while using each of the three available clock sources. if a sleep instruction is executed and slpen = 0 , the module will continue to display the current contents of the lcddata registers. to allow the module to continue operation while in sleep, the clock source must be either the lfintosc or t1osc external oscillator. while in sleep, the lcd data cannot be changed. the lcd module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shut down of the core and other peripheral functions. table 19-8 shows the status of the lcd module during sleep while using each of the three available clock sources: table 19-8: lcd module status during sleep if lcd interrupts are being generated (type-b wave- form with a multiplex mode not static) and lcdie = 1 , the device will awaken from sleep on the next frame boundary. note: when the lcden bit is cleared, the lcd module will be disabled at the completion of frame. at this time, the port pins will revert to digital functionality. to minimize power consumption due to floating digital inputs, the lcd pins should be driven low using the port and tris registers. clock source slpen operational during sleep t1osc 0 yes 1 no lfintosc 0 yes 1 no f osc /4 0 no 1 no note: the lfintosc or external t1osc oscillator must be used to operate the lcd module during sleep.
pic16lf1904/6/7 ds41569a-page 216 preliminary ? 2011 microchip technology inc. figure 19-20: sleep entry/exit when slpen = 1 sleep instruction execution wake-up 2 frames v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 com0 com1 com2 seg0
? 2011 microchip technology inc. preliminary ds41569a-page 217 pic16lf1904/6/7 19.12 configuring the lcd module the following is the sequence of steps to configure the lcd module. 1. select the frame clock prescale using bits lp<3:0> of the lcdps register. 2. configure the appropriate pins to function as segment drivers using the lcdsen registers. 3. configure the lcd module for the following using the lcdcon register: - multiplex and bias mode, bits lmux<1:0> - timing source, bits cs<1:0> - sleep mode, bit slpen 4. write initial values to pixel data registers, lcddata0 through lcddata21. 5. clear lcd interrupt flag, lcdif bit of the pir2 register and if desired, enable the interrupt by setting bit lcdie of the pie2 register. 6. configure bias voltages by setting the lcdrl, lcdref and the associated anselx registers as needed. 7. enable the lcd module by setting bit lcden of the lcdcon register. 19.13 disabling the lcd module to disable the lcd module, write all ? 0 ?s to the lcdcon register. 19.14 lcd current consumption when using the lcd module the current consumption consists of the following three factors: ? oscillator selection ? lcd bias source ? capacitance of the lcd segments the current consumption of just the lcd module can be considered negligible compared to these other factors. 19.14.1 oscillator selection the current consumed by the clock source selected must be considered when using the lcd module. see section 22.0 ?electrical specifications? for oscillator current consumption information. 19.14.2 lcd bias source the lcd bias source, internal or external, can contrib- ute significantly to the current consumption. use the highest possible resistor values while maintaining contrast to minimize current. 19.14.3 capacitance of the lcd segments the lcd segments which can be modeled as capaci- tors which must be both charged and discharged every frame. the size of the lcd segment and its technology determines the segment?s capacitance.
pic16lf1904/6/7 ds41569a-page 218 preliminary ? 2011 microchip technology inc. table 19-9: summary of registers associated with lcd operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 lcdcon lcden slpen werr ? cs1 cs0 lmux<1:0> 187 lcdcst ? ? ? ? ? lcdcst<2:0> 190 lcddata0 seg7 com0 seg6 com0 seg5 com0 seg4 com0 seg3 com0 seg2 com0 seg1 com0 seg0 com0 191 lcddata1 seg15 com0 seg14 com0 seg13 com0 seg12 com0 seg11 com0 seg10 com0 seg9 com0 seg8 com0 191 lcddata2 seg23 com0 seg22 com0 seg21 com0 seg20 com0 seg19 com0 seg18 com0 seg17 com0 seg16 com0 191 lcddata3 seg7 com1 seg6 com1 seg5 com1 seg4 com1 seg3 com1 seg2 com1 seg1 com1 seg0 com1 191 lcddata4 seg15 com1 seg14 com1 seg13 com1 seg12 com1 seg11 com1 seg10 com1 seg9 com1 seg8 com1 191 lcddata5 seg23 com1 seg22 com1 seg21 com1 seg20 com1 seg19 com1 seg18 com1 seg17 com1 seg16 com1 191 lcddata6 seg7 com2 seg6 com2 seg5 com2 seg4 com2 seg3 com2 seg2 com2 seg1 com2 seg0 com2 191 lcddata7 seg15 com2 seg14 com2 seg13 com2 seg12 com2 seg11 com2 seg10 com2 seg9 com2 seg8 com2 191 lcddata8 seg23 com2 seg22 com2 seg21 com2 seg20 com2 seg19 com2 seg18 com2 seg17 com2 seg16 com2 191 lcddata9 seg7 com3 seg6 com3 seg5 com3 seg4 com3 seg3 com3 seg2 com3 seg1 com3 seg0 com3 191 lcddata10 seg15 com3 seg14 com3 seg13 com3 seg12 com3 seg11 com3 seg10 com3 seg9 com3 seg8 com3 191 lcddata11 seg23 com3 seg22 com3 seg20 com3 seg19 com3 seg18 com3 seg17 com3 seg16 com3 seg15 com3 191 lcddata12 ? ? ?seg28 com0 seg27 com0 seg26 com0 seg25 com0 seg24 com0 191 lcddata15 ? ? ?seg28 com1 seg27 com1 seg26 com1 seg25 com1 seg24 com1 191 lcddata18 ? ? ?seg28 com2 seg27 com2 seg26 com2 seg25 com2 seg24 com2 191 lcddata21 ? ? ?seg28 com3 seg27 com3 seg26 com3 seg25 com3 seg24 com3 191 lcdps wft biasmd lcda wa lp<3:0> 188 lcdref lcdire ? lcdiri ? vlcd3pe vlcd2pe vlcd1pe ? 189 lcdrl lrlap<1:0> lrlbp<1:0> ?lrlat<2:0> 198 lcdse0 se<7:0> 191 lcdse1 se<15:8> 191 lcdse2 se<23:16> 191 lcdse3 ? ? ? se<28:24> 191 pie2 ? ? ? ? ?lcdie ? ? 74 pir2 ? ? ? ? ? lcdif ? ? 76 t1con tmr1cs1 tmr1cs0 t1ckps1 t1ckps0 t1oscen t1sync ? tmr1on 151 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the lcd module.
? 2011 microchip technology inc. preliminary ds41569a-page 219 pic16lf1904/6/7 20.0 in-circuit serial programming? (icsp?) icsp? programming allows customers to manufacture circuit boards with unprogrammed devices. programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. five pins are needed for icsp? programming: ? icspclk ? icspdat ?mclr /v pp ?v dd ?v ss in program/verify mode the program memory, user ids and the configuration words are programmed through serial communications. the icspdat pin is a bidirectional i/o used for transferring the serial data and the icspclk pin is the clock input. for more information on icsp? refer to the ? pic16f193x/lf193x/pic16f194x/lf194x/pic16lf 190x memory programming specification ? (ds41397). 20.1 high-voltage programming entry mode the device is placed into high-voltage programming entry mode by holding the icspclk and icspdat pins low then raising the voltage on mclr /v pp to v ihh . some programmers produce v pp greater than v ihh (9.0v), an external circuit is required to limit the v pp voltage. see figure 20-1 for example circuit. figure 20-1: v pp limiter example circuit v ref v pp v dd v ss icsp_data icsp_clock nc rj11-6pin rj11-6pin r1 270 ohm to m p l a b ? icd 2 to tar g e t b o ar d 1 2 3 4 5 61 2 3 4 5 6 r2 r3 10k 1% 24k 1% u1 lm431bcmx a 2 3 6 7 8 a a a k nc nc 1 4 5 note: the mplab ? icd 2 produces a v pp voltage greater than the maximum v pp specification of the pic16lf1904/6/7.
pic16lf1904/6/7 ds41569a-page 220 preliminary ? 2011 microchip technology inc. 20.2 low-voltage programming entry mode the low-voltage programming entry mode allows the pic16lf1904/6/7 devices to be programmed using v dd only, without high voltage. when the lvp bit of configuration word 2 is set to ? 1 ?, the low-voltage icsp programming entry is enabled. to disable the low-voltage icsp mode, the lvp bit must be programmed to ? 0 ?. entry into the low-voltage programming entry mode requires the following steps: 1. mclr is brought to v il . 2. a 32-bit key sequence is presented on icspdat, while clocking icspclk. once the key sequence is complete, mclr must be held at v il for as long as program/verify mode is to be maintained. if low-voltage programming is enabled (lvp = 1 ), the mclr reset function is automatically enabled and cannot be disabled. see section 5.3 ?ultra low-power brown-out reset (ulpbor)? for more information. the lvp bit can only be reprogrammed to ? 0 ? by using the high-voltage programming mode. 20.3 common programming interfaces connection to a target device is typically done through an icsp? header. a commonly found connector on development tools is the rj-11 in the 6p6c (6-pin, 6-connector) configuration. see figure 20-2 . figure 20-2: icd rj-11 style connector interface another connector often found in use with the pickit? programmers is a standard 6-pin header with 0.1 inch spacing. refer to figure 20-3 . figure 20-3: pickit? styl e connector interface 1 2 3 4 5 6 target bottom side pc board v pp /mclr v ss icspclk v dd icspdat nc pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect 1 2 3 4 5 6 * the 6-pin header (0.100" spacing) accepts 0.025" square pins. pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect pin 1 indicator
? 2011 microchip technology inc. preliminary ds41569a-page 221 pic16lf1904/6/7 for additional interface recommendations, refer to your specific device programmer manual prior to pcb design. it is recommended that isolation devices be used to separate the programming pins from other circuitry. the type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. see figure 20-4 for more information. figure 20-4: typical connect ion for icsp? programming v dd v pp v ss external device to be data clock v dd mclr /v pp v ss icspdat icspclk * * * to normal connections * isolation devices (as required). programming signals programmed v dd
pic16lf1904/6/7 ds41569a-page 222 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 223 pic16lf1904/6/7 21.0 instruction set summary each pic16 instruction is a 14-bit word containing the operation code (opcode) and all required operands. the opcodes are broken into three broad categories. ? byte oriented ? bit oriented ? literal and control the literal and control category contains the most var- ied instruction word format. table 21-3 lists the instructions recognized by the mpasm tm assembler. all instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: ? subroutine takes two cycles ( call , callw ) ? returns from interrupts or subroutines take two cycles ( return , retlw , retfie ) ? program branching takes two cycles ( goto , bra , brw , btfss , btfsc , decfsz , incsfz ) ? one additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. one instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 mhz, this gives a nominal instruction execution rate of 1 mhz. all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 21.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. table 21-1: opcode field descriptions table 21-2: abbreviation descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w , d = 1 : store result in file register f. default is d = 1 . n fsr or indf number. (0-1) mm pre-post increment-decrement mode selection field description pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit
pic16lf1904/6/7 ds41569a-page 224 preliminary ? 2011 microchip technology inc. figure 21-1: general format for instructions byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only movlp instruction only 13 5 4 0 opcode k (literal) k = 5-bit immediate value movlb instruction only 13 9 8 0 opcode k (literal) k = 9-bit immediate value bra instruction only fsr offset instructions 13 7 6 5 0 opcode n k (literal) n = appropriate fsr fsr increment instructions 13 7 6 0 opcode k (literal) k = 7-bit immediate value 13 3 2 1 0 opcode n m (mode) n = appropriate fsr m = 2-bit mode value k = 6-bit immediate value 13 0 opcode opcode only
? 2011 microchip technology inc. preliminary ds41569a-page 225 pic16lf1904/6/7 table 21-3: pic16lf1904/6/7 enhanced instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf asrf lslf lsrf clrf clrw comf decf incf iorwf movf movwf rlf rrf subwf subwfb swapf xorwf f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d add w and f add with carry w and f and w with f arithmetic right shift logical left shift logical right shift clear f clear w complement f decrement f increment f inclusive or w with f move f move w to f rotate left f through carry rotate right f through carry subtract w from f subtract with borrow w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z c, dc, z z c, z c, z c, z z z z z z z z c c c, dc, z c, dc, z z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 byte oriented skip operations decfsz incfsz f, d f, d decrement f, skip if 0 increment f, skip if 0 1(2) 1(2) 00 00 1011 1111 dfff dfff ffff ffff 1, 2 1, 2 bit-oriented file register operations bcf bsf f, b f, b bit clear f bit set f 1 1 01 01 00bb 01bb bfff bfff ffff ffff 2 2 bit-oriented skip operations btfsc btfss f, b f, b bit test f, skip if clear bit test f, skip if set 1 (2) 1 (2) 01 01 10bb 11bb bfff bfff ffff ffff 1, 2 1, 2 literal operations addlw andlw iorlw movlb movlp movlw sublw xorlw k k k k k k k k add literal and w and literal with w inclusive or literal with w move literal to bsr move literal to pclath move literal to w subtract w from literal exclusive or literal with w 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z z z c, dc, z z note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle.
pic16lf1904/6/7 ds41569a-page 226 preliminary ? 2011 microchip technology inc. table 21-3: pic16lf1904/6/7 enhanced instruction set (continued) mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb control operations bra brw call callw goto retfie retlw return k ? k ? k k k ? relative branch relative branch with w call subroutine call subroutine with w go to address return from interrupt return with literal in w return from subroutine 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 inherent operations clrwdt nop option reset sleep tris ? ? ? ? ? f clear watchdog timer no operation load option_reg register with w software device reset go into standby mode load tris register with w 1 1 1 1 1 1 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 0000 0010 0001 0011 0fff to , pd to , pd c-compiler optimized addfsr moviw movwi n, k n mm k[n] n mm k[n] add literal k to fsrn move indirect fsrn to w with pre/post inc/dec modifier, mm move indfn to w, indexed indirect. move w to indirect fsrn with pre/post inc/dec modifier, mm move w to indfn, indexed indirect. 1 1 1 1 1 11 00 11 00 11 0001 0000 1111 0000 1111 0nkk 0001 0nkk 0001 1nkk kkkk 0nmm kkkk 1nmm kkkk z z 2, 3 2 2, 3 2 note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle. 3: see table in the moviw and movwi instruction descriptions.
? 2011 microchip technology inc. preliminary ds41569a-page 227 pic16lf1904/6/7 21.2 instruction descriptions addfsr add literal to fsrn syntax: [ label ] addfsr fsrn, k operands: -32 ? k ? 31 n ? [ 0, 1] operation: fsr(n) + k ? fsr(n) status affected: none description: the signed 6-bit literal ?k? is added to the contents of the fsrnh:fsrnl register pair. fsrn is limited to the range 0000h - ffffh. moving beyond these bounds will cause the fsr to wrap-around. addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. addwfc add w and carry bit to f syntax: [ label ] addwfc f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: c, dc, z description: add w, the carry flag and data mem- ory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. asrf arithmetic right shift syntax: [ label ] asrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. the msb remains unchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in reg- ister ?f?. register f c
pic16lf1904/6/7 ds41569a-page 228 preliminary ? 2011 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit ?b? in register ?f? is cleared. bra relative branch syntax: [ label ] bra label [ label ] bra $+k operands: -256 ? label - pc + 1 ? 255 -256 ? k ? 255 operation: (pc) + 1 + k ? pc status affected: none description: add the signed 9-bit literal ?k? to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + k. this instruction is a two-cycle instruc- tion. this branch has a limited range. brw relative branch with w syntax: [ label ] brw operands: none operation: (pc) + (w) ? pc status affected: none description: add the contents of w (unsigned) to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + (w). this instruction is a two-cycle instruc- tion. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b?, in register ?f?, is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a 2-cycle instruction. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruction is discarded and a nop is executed instead, making this a 2-cycle instruction.
? 2011 microchip technology inc. preliminary ds41569a-page 229 pic16lf1904/6/7 call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<6:3>) ? pc<14:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruc- tion. callw subroutine call with w syntax: [ label ] callw operands: none operation: (pc) +1 ? tos, (w) ? pc<7:0>, (pclath<6:0>) ?? pc<14:8> status affected: none description: subroutine call with w. first, the return address (pc + 1) is pushed onto the return stack. then, the con- tents of w is loaded into pc<7:0>, and the contents of pclath into pc<14:8>. callw is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f ) ? (destination) status affected: z description: the contents of register ?f? are com- plemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
pic16lf1904/6/7 ds41569a-page 230 preliminary ? 2011 microchip technology inc. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<6:3> ? pc<14:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination) status affected: z description: the contents of register ?f? are incre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with regis- ter ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
? 2011 microchip technology inc. preliminary ds41569a-page 231 pic16lf1904/6/7 lslf logical left shift syntax: [ label ] lslf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? c (f<6:0>) ? dest<7:1> 0 ? dest<0> status affected: c, z description: the contents of register ?f? are shifted one bit to the left through the carry flag. a ? 0 ? is shifted into the lsb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. lsrf logical right shift syntax: [ label ] lslf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: 0 ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. a ? 0 ? is shifted into the msb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. register f 0 c register f c 0 movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) ? (dest) status affected: z description: the contents of register f is moved to a destination dependent upon the status of d. if d = 0 , destination is w register. if d = 1 , the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register z= 1
pic16lf1904/6/7 ds41569a-page 232 preliminary ? 2011 microchip technology inc. moviw move indfn to w syntax: [ label ] moviw ++fsrn [ label ] moviw --fsrn [ label ] moviw fsrn++ [ label ] moviw fsrn-- [ label ] moviw k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: indfn ? w effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) ? unchanged status affected: z mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. movlb move literal to bsr syntax: [ label ] movlb k operands: 0 ? k ? 15 operation: k ? bsr status affected: none description: the five-bit literal ?k? is loaded into the bank select register (bsr). movlp move literal to pclath syntax: [ label ] movlp k operands: 0 ? k ? 127 operation: k ? pclath status affected: none description: the seven-bit literal ?k? is loaded into the pclath register. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the ?don?t cares? will assem- ble as ? 0 ?s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register ?f?. words: 1 cycles: 1 example: movwf option_reg before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f
? 2011 microchip technology inc. preliminary ds41569a-page 233 pic16lf1904/6/7 movwi move w to indfn syntax: [ label ] movwi ++fsrn [ label ] movwi --fsrn [ label ] movwi fsrn++ [ label ] movwi fsrn-- [ label ] movwi k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: w ? indfn effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) unchanged status affected: none mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. the increment/decrement operation on fsrn will not affect any status bits. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. words: 1 cycles: 1 example: nop option load option_reg register with w syntax: [ label ] option operands: none operation: (w) ? option_reg status affected: none description: move data from w register to option_reg register. words: 1 cycles: 1 example: option before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f reset software reset syntax: [ label ] reset operands: none operation: execute a device reset. resets the nri flag of the pcon register. status affected: none description: this instruction provides a way to execute a hardware reset by soft- ware.
pic16lf1904/6/7 ds41569a-page 234 preliminary ? 2011 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example: table call table;w contains table ;offset value ? ;w now has table value ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c=0 after instruction reg1 = 1110 0110 w = 1100 1100 c=1 register f c
? 2011 microchip technology inc. preliminary ds41569a-page 235 pic16lf1904/6/7 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. sleep enter sleep mode syntax: [ label ]sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2?s com- plement method) from the eight-bit literal ?k?. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [ 0 , 1 ] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f. subwfb subtract w from f with borrow syntax: subwfb f {,d} operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (w) ? (b ) ?? dest status affected: c, dc, z description: subtract w and the borrow flag (carry) from register ?f? (2?s comple- ment method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. c = 0 w ? k c = 1 w ? k dc = 0 w<3:0> ? k<3:0> dc = 1 w<3:0> ? k<3:0> c = 0 w ? f c = 1 w ? f dc = 0 w<3:0> ? f<3:0> dc = 1 w<3:0> ? f<3:0>
pic16lf1904/6/7 ds41569a-page 236 preliminary ? 2011 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of regis- ter ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. tris load tris register with w syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register ?f? status affected: none description: move data from w register to tris register. when ?f? = 5, trisa is loaded. when ?f? = 6, trisb is loaded. when ?f? = 7, trisc is loaded. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in regis- ter ?f?.
? 2011 microchip technology inc. preliminary ds41569a-page 237 pic16lf1904/6/7 22.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias................................................................................................. ...... -40c to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss ................................................................................................... -0.3v to +4.0v voltage on mclr with respect to vss ................................................................................................. -0.3v to +9.0v voltage on all other pins with respect to v ss ........................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... 800 mw maximum current out of v ss pin, -40c ? t a ? +85c for industrial............................................................... 300 ma maximum current out of v ss pin, -40c ? t a ? +125c for extended .............................................................. 95 ma maximum current into v dd pin, -40c ? t a ? +85c for industrial.................................................................. 250 ma maximum current into v dd pin, -40c ? t a ? +125c for extended ................................................................. 70 ma clamp current, i k (v pin < 0 or v pin > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????? 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 25 ma maximum output current sourced by any i/o pin .................................................................................. ............ 25 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v o l x i ol ). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure above maximum rating conditions for extended periods may affect device reliability.
pic16lf1904/6/7 ds41569a-page 238 preliminary ? 2011 microchip technology inc. figure 22-1: voltage frequency graph, -40c ? t a ?? +125c figure 22-2: hfintosc frequency accuracy over device v dd and temperature 1.8 2.5 2.0 0 2.3 frequency (mhz) v dd (v) note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 22-1 for each oscillator mode?s supported frequencies. 4 10 16 3.6 20 internal oscillator or ec mode ec mode only 125 25 2.0 0 60 85 v dd (v) 3.6 temperature ( c ) 2.5 3.0 3.5 1.8 -40 -20 + 15% 10% + 15%
? 2011 microchip technology inc. preliminary ds41569a-page 239 pic16lf1904/6/7 figure 22-3: por and por rearm with slow rising v dd 22.1 dc characteristics: pic16lf1904/6/7-i/e (industrial, extended) pic16lf1904/6/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. sym. characteristic min. typ? max. units conditions supply voltage d001 v dd 1.8 ? 3.6 v f osc ? 16 mhz: d002* v dr ram data retention voltage (1) 1.5 ? ? v device in sleep mode d002a* v por * power-on reset release voltage ?1.6? v d002b* v porr * power-on reset rearm voltage ? 1.7 ? v device in sleep mode d003 v adfvr fixed voltage reference voltage for adc, initial accuracy 6 7 7 8 ? ? ? ? 4 4 6 6 %1.024v, v dd ? 1.8v, 85c 1.024v, v dd ? 1.8v, 125c 2.048v, v dd ? 2.5v, 85c 2.048v, v dd ? 2.5v, 125c d003a v cdafvr fixed voltage reference voltage for comparator and dac, initial accu- racy 7 8 8 9 ? ? ? ? 5 5 7 7 %1.024v, v dd ? 1.8v, 85c 1.024v, v dd ? 1.8v, 125c 2.048v, v dd ? 2.5v, 85c 2.048v, v dd ? 2.5v, 125c d003b v lcdfvr fixed voltage reference voltage for lcd bias, initial accuracy 9 9.5 ? ? 9 9 %3.072v, v dd ? 3.6v, 85c 3.072v, v dd ? 3.6v, 125c d003c* tcv fvr temperature coefficient, fixed volt- age reference ? -130 ? ppm/c d003d* ? v fvr / ? v in line regulation, fixed voltage ref- erence ? 0.270 ? %/v d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 5.1 ?power-on reset (por)? for details. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.3v, 25c unless otherwise stated. these parameters are for design guidance only and are not teste d. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. v dd v por v porr v ss v ss npor t por (3) por rearm note 1: when npor is low, the device is held in reset. 2: t por 1 ? s typical. 3: t vlow 2.7 ? s typical. t vlow (2)
pic16lf1904/6/7 ds41569a-page 240 preliminary ? 2011 microchip technology inc. 22.2 dc characteristics: pic16lf1904/6/7-i/e (industrial, extended) pic16lf1904/6/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note supply current (i dd ) (1, 2) d010 ? 45 75 ? a1.8f osc = 1 mhz ec oscillator mode high power mode ? 80 140 ? a3.0 ? 100 160 ? a3.6 d011 ? 130 200 ? a1.8f osc = 4 mhz ec oscillator mode high power mode ? 225 300 ? a3.0 ? 260 350 ? a3.6 d011a ? 2.67 8 ? a1.8f osc = 32 khz lfintosc mode ?4.1 12 ? a3.0 ?4.6 20 ? a3.6 d012 ? 200 275 ? a1.8f osc = 500 khz hfintosc mode ? 260 375 ? a3.0 ? 300 395 ? a3.6 d013 ? 225 tbd ? a1.8f osc = 1 mhz hfintosc mode ? 290 tbd ? a3.0 ? 325 tbd ? a3.6 d014 ? 300 tbd ma 1.8 f osc = 4 mhz hfintosc mode ? 415 tbd ma 3.0 ? 480 tbd ma 3.6 d015 ? 0.4 0.9 ma 1.8 f osc = 8 mhz hfintosc mode ? 0.5 1 ma 3.0 ? 0.6 1.1 ma 3.6 d016 ? 0.8 1.5 ma 1.8 f osc = 16 mhz hfintosc mode ? 0.9 1.6 ma 3.0 ? 1.0 1.7 ma 3.6 note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: fvr and bor are disabled.
? 2011 microchip technology inc. preliminary ds41569a-page 241 pic16lf1904/6/7 22.3 dc characteristics: pic16lf1904/6/7-i/e (power-down) pic16lf1904/6/7 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note power-down base current (i pd ) (2) d023 ? 0.03 1.0 3.0 ? a 1.8 wdt, bor, fvr, and t1osc disabled, all peripherals inactive ? 0.04 2.0 4.0 ? a3.0 ? 0.09 3.0 5.0 ? a3.6 d024 ? 0.3 2.0 4.0 ? a 1.8 lpwdt current (note 1) ? 0.5 3.0 5.0 ? a3.0 ? 0.6 4.0 6.0 ? a3.6 d025 ?20 31 35 ? a 1.8 fvr current ?22 41 45 ? a3.0 ?24 46 50 ? a3.6 d026 ? 121 300 560 na 3.0 lpbor current (note 1) ? 141 400 700 na 3.6 d027 ? 7.5 16 32 ? a 3.0 bor current (note 1) ? 8.0 18 34 ? a3.6 d028 ? 0.5 2.0 4.0 ? a 1.8 t1osc current (note 1) ? 0.6 3.0 5.0 ? a3.0 ? 0.7 4.0 6.0 ? a3.6 d029 ? 0.4 2.0 4.0 ? a 1.8 a/d current (note 1, note 3) , no conversion in progress ? 0.7 3.0 5.0 ? a3.0 ? 0.9 4.0 6.0 ? a3.6 d030 ? ? 250 ? ? a 1.8 a/d current (note 1, note 3) , conversion in progress ? ? 250 ? ? a3.0 ? ? 250 ? ? a3.6 d031 lcd bias ladder low power ? 1 5 6 ? a3.6 medium power ? 10 16 21 ? a3.6 high power ? 100 110 120 ? a3.6 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. legend: tbd = to be determined note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: a/d oscillator source is f rc .
pic16lf1904/6/7 ds41569a-page 242 preliminary ? 2011 microchip technology inc. 22.4 dc characteristics: pic16lf1904/6/7-i/e dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions v il input low voltage i/o port: d032 with ttl buffer ? ? 0.15 v dd v1.8v ? v dd ? 3.6v d033 with schmitt trigger buffer ? ? 0.2 v dd v1.8v ? v dd ? 3.6v d034 mclr , osc1 ? ? 0.2 v dd v v ih input high voltage i/o ports: d040 with ttl buffer 0.25 v dd + 0.8 ??v1.8v ? v dd ? 3.6v d041 with schmitt trigger buffer 0.8 v dd ??v1.8v ? v dd ? 3.6v d042 mclr 0.8 v dd ??v i il input leakage current (2) d060 i/o ports ? 5 5 125 1000 na na v ss ? v pin ? v dd , pin at high- impedance @ 85c 125c d061 mclr (3) ? 50 200nav ss ? v pin ? v dd @ 85c i pur weak pull-up current d070* 25 100 200 ? av dd = 3.3v, v pin = v ss v ol output low voltage d080 i/o ports ? ?0.6v i ol = 6ma, v dd = 3.3v i ol = 1.8ma, v dd = 1.8v v oh output high voltage d090 i/o ports v dd - 0.7 ? ? v i oh = 3ma, v dd = 3.3v i oh = 1ma, v dd = 1.8v capacitive loading specs on output pins d101* c io all i/o pins ? ? 50 pf * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: negative current is defined as current sourced by the pin.
? 2011 microchip technology inc. preliminary ds41569a-page 243 pic16lf1904/6/7 22.5 memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions program memory programming specifications d110 v ihh voltage on mclr /v pp /re3 pin 8.0 ? 9.0 v (note 2, note 3) d111 i ddp supply current during programming ??10ma d112 v dd for bulk erase 2.7 ? v dd max. v d113 v pew v dd for write or row erase v dd min. ?v dd max. v d114 i pppgm current on mclr /v pp during erase/ write ??1.0ma d115 i ddpgm current on v dd during erase/write ? 5.0 ma program flash memory d121 e p cell endurance 10k ? ?e/w-40 ? c to +85 ? c ( note 1 ) d122 v pr v dd for read v dd min. ?v dd max. v d123 t iw self-timed write cycle time ? 2 2.5 ms d124 t retd characteristic retention 40 ? ? year provided no other specifications are violated ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: self-write and block erase. 2: required only if single-supply programming is disabled. 3: the mplab icd 2 does not support variable v pp output. circuitry to limit the icd 2 v pp voltage must be placed between the icd 2 and target system when programming or debugging with the icd 2.
pic16lf1904/6/7 ds41569a-page 244 preliminary ? 2011 microchip technology inc. 22.6 thermal considerations standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic typ. units conditions th01 ? ja thermal resistance junction to ambient 60 ? c/w 28-pin spdip package 80 ? c/w 28-pin soic package 90 ? c/w 28-pin ssop package 27.5 ? c/w 28-pin uqfn 4x4mm package th02 ? jc thermal resistance junction to case 31.4 ? c/w 28-pin spdip package 24 ? c/w 28-pin soic package 24 ? c/w 28-pin ssop package 24 ? c/w 28-pin uqfn 4x4mm package th03 t jmax maximum junction temperature 150 ? c th04 pd power dissipation ? w pd = p internal + p i / o th05 p internal internal power dissipation ? w p internal = i dd x v dd (1) th06 p i / o i/o power dissipation ? w p i / o = ? (i ol * v ol ) + ? (i oh * (v dd - v oh )) th07 p der derated power ? w p der = pd max (t j - t a )/ ? ja (2) note 1: i dd is current to run the chip alone without driving any load on the output pins. 2: t a = ambient temperature 3: t j = junction temperature
? 2011 microchip technology inc. preliminary ds41569a-page 245 pic16lf1904/6/7 22.7 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 22-4: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance v ss c l legend: c l = 50 pf for all pins, 15 pf for osc2 output load condition pin
pic16lf1904/6/7 ds41569a-page 246 preliminary ? 2011 microchip technology inc. 22.8 ac characteristics: pic16lf1904/6/7-i/e table 22-1: clock oscillator timing requirements table 22-2: oscillator parameters standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions os01 f osc external clkin frequency (1) dc ? 0.5 mhz ec oscillator mode (low) dc ? 4 mhz ec oscillator mode (medium) dc ? 32 mhz ec oscillator mode (high) os02 t osc external clkin period (1) 31.25 ? ? ns ec oscillator mode os03 t cy instruction cycle time (1) 200 t cy dc ns t cy = 4/f osc * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at ?min? values wi th an external clock applied to osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic freq. tolerance min. typ? max. units conditions os08 hf osc internal calibrated hfintosc frequency (2) ? 10% ? 16.0 ? mhz 0c ? t a ? +85c, v dd ?? 2.5v ? 15% ? 16.0 ? mhz -40c ? t a ? +125c, v dd ?? 2.5v os08a mf osc internal calibrated mfintosc frequency (2) ? 10% ? 500 ? khz 0c ? t a ? +85c ? 15% ? 500 ? khz -40c ? t a ? +125c os10* t iosc st hfintosc wake-up from sleep start-up time mfintosc wake-up from sleep start-up time ??58 ? s ? ? 20 30 ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator ty pe under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min? values with an external clock applied to the osc1 pin. when an external clock input is used, the ?max? cycle ti me limit is ?dc? (no clock) for all devices. 2: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended.
? 2011 microchip technology inc. preliminary ds41569a-page 247 pic16lf1904/6/7 figure 22-5: clkout and i/o timing table 22-3: clkout and i/o timing parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions os11 tosh2ckl f osc ? to clkout ? (1) ??70nsv dd = 3.3-5.0v os12 tosh2ckh f osc ? to clkout ? (1) ??72nsv dd = 3.3-5.0v os13 tckl2iov clkout ? to port out valid (1) ??20ns os14 tiov2ckh port input valid before clkout ? (1) t osc + 200 ns ? ? ns os15 tosh2iov fosc ? (q1 cycle) to port out valid ? 50 70* ns v dd = 3.3-5.0v os16 tosh2ioi fosc ? (q2 cycle) to port input invalid (i/o in hold time) 50 ? ? ns v dd = 3.3-5.0v os17 tiov2osh port input valid to fosc ?? (q2 cycle) (i/o in setup time) 20 ? ? ns os18 tior port output rise time ? ? 40 15 72 32 ns v dd = 1.8v v dd = 3.3-5.0v os19 tiof port output fall time ? ? 28 15 55 30 ns v dd = 1.8v v dd = 3.3-5.0v os20* tinp int pin input high or low time 25 ? ? ns os21* tioc interrupt-on-change new input level time 25 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25 ? c unless otherwise stated. note 1: measurements are taken in ec mode where clkout output is 4 x t osc . f osc clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 os11 os19 os13 os15 os18, os19 os20 os21 os17 os16 os14 os12 os18 old value new value write fetch read execute cycle
pic16lf1904/6/7 ds41569a-page 248 preliminary ? 2011 microchip technology inc. figure 22-6: reset, watchdog timer, os cillator start-up timer and power-up timer timing figure 22-7: brown-out rese t timing and characteristics v dd mclr internal por pwrt time-out osc start-up time internal reset (1) watchdog timer 33 32 30 31 34 i/o pins 34 note 1: asserted low. reset (1) v bor v dd (device in brown-out reset) (device not in brown-out reset) 33 (1) note 1: 64 ms delay only if pwrte bit in the configuration word register is programmed to ? 0 ?. 2 ms delay if pwrte = 0 and vregen = 1 . reset (due to bor) v bor and v hyst 37
? 2011 microchip technology inc. preliminary ds41569a-page 249 pic16lf1904/6/7 figure 22-8: minimum pulse wi dth for lpbor detection v ddio v ulpbor (monitored voltage) v bpw < 10 nvs 10 nvs < v bpw < 500 nvs 500 nvs < v bpw maybe detected pulse rejected
pic16lf1904/6/7 ds41569a-page 250 preliminary ? 2011 microchip technology inc. table 22-4: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset parameters figure 22-9: timer0 and time r1 external clock timings standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 30 t mc lmclr pulse width (low) 2 5 ? ? ? ? ? s ? s v dd = 3.3-5v, -40c to +85c v dd = 3.3-5v 31 t wdtlp low-power watchdog timer time-out period (no prescaler) 10 18 27 ms v dd = 3.3v-5v 32 t ost oscillator start-up timer period (1) ? 1024 ? tosc (note 2) 33* t pwrt power-up timer period, pwrte = 0 40 65 140 ms 34* t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0 ? s 35 v bor brown-out reset voltage 2.38 1.80 2.5 1.9 2.73 2.11 vborv=2.5v borv=1.9v 36* v hyst brown-out reset hysteresis 0 25 50 mv -40c to +85c 37* t bordc brown-out reset dc response time 135 ? sv dd ? v bor * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices ar e tested to operate at ?min? values with an external clock applied to the osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: period of the slower clock. 3: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. t0cki t1cki 40 41 42 45 46 47 49 tmr0 or tmr1
? 2011 microchip technology inc. preliminary ds41569a-page 251 pic16lf1904/6/7 table 22-5: timer0 and timer1 external clock requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 42* t t 0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 46* t t 1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 47* t t 1p t1cki input period synchronous greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ? ns 48 f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) 32.4 32.768 33.1 khz 49* tckez tmr 1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? timers in sync mode * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16lf1904/6/7 ds41569a-page 252 preliminary ? 2011 microchip technology inc. table 22-6: pic16lf1904/6/7 a/d converter (adc) characteristics : table 22-7: pic16lf1904/6/7 a/d conversion requirements standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ad01 n r resolution ? ? 10 bit ad02 e il integral error ? ? 1.7 lsb v ref = 3.0v ad03 e dl differential error ? ? 1 lsb no missing codes v ref = 3.0v ad04 e off offset error ? ? 2 lsb v ref = 3.0v ad05 e gn gain error ? ? 1.5 lsb v ref = 3.0v ad06 v ref reference voltage (3) 1.8 ? v dd v ad07 v ain full-scale range v ss ?v ref v ad08 z ain recommended impedance of analog voltage source ?? 50 k ? can go higher if external 0.01 ? f capacitor is present on input pin. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 3: adc v ref is from external v ref , v dd pin or fv ref , whichever is selected as reference input. 4: when adc is off, it will not consume any current other than leakage current. the power-down current specification includes any such leakage from the adc module. standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ad130* t ad a/d clock period 1.0 ? 9.0 ? st osc -based a/d internal rc oscillator period 1.0 1.6 6.0 ? s adcs<1:0> = 11 (adrc mode) ad131 t cnv conversion time (not including acquisition time) (1) ?11?t ad set go/done bit to conversion complete ad132* t acq acquisition time ? 5.0 ? ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the adres register may be read on the following t cy cycle.
? 2011 microchip technology inc. preliminary ds41569a-page 253 pic16lf1904/6/7 figure 22-10: pic16lf1904/6/7 a/d co nversion timing (normal mode) figure 22-11: pic16lf1904/6/7 a/d conversion timing (sleep mode) ad131 ad130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 765 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 4 (t osc /2 (1) ) 1 t cy ad132 ad132 ad131 ad130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 7 5 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 4 6 1 t cy (t osc /2 + t cy (1) ) 1 t cy
pic16lf1904/6/7 ds41569a-page 254 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 255 pic16lf1904/6/7 23.0 dc and ac characteristics graphs and charts graphs and charts are not available at this time.
pic16lf1904/6/7 ds41569a-page 256 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 257 pic16lf1904/6/7 24.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 24.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic16lf1904/6/7 ds41569a-page 258 preliminary ? 2011 microchip technology inc. 24.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 24.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 24.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 24.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 24.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2011 microchip technology inc. preliminary ds41569a-page 259 pic16lf1904/6/7 24.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 24.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 24.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 24.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
pic16lf1904/6/7 ds41569a-page 260 preliminary ? 2011 microchip technology inc. 24.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 24.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 24.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits.
? 2011 microchip technology inc. preliminary ds41569a-page 261 pic16lf1904/6/7 25.0 packaging information 25.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead pdip xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxxxx example pic16lf1906-i/p 1048017 28-lead soic (.300?) xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example pic16lf1906-e/so 1048017 3 e 28-lead uqfn (4x4x0.5 mm) example xxxxx ywwnnn xxxxxx xxxxxx pic16 048017 lf1906 e/mv 3 e 28-lead ssop (.209?) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic16lf1906 -e/ss 1048017 3 e
pic16lf1904/6/7 ds41569a-page 262 preliminary ? 2011 microchip technology inc. package marking information (continued) 3 e xxxxxxx 40-lead uqfn (5x5mm) xxxxxxx xxxxxxx yywwnnn example 16f1904 -i/mv 1010017 3 e 40-lead pdip (.600?) xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx yywwnnn example -i/p pic16f1904 1010017 44-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic16f1907 -e/pt 1048017 3 e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2011 microchip technology inc. preliminary ds41569a-page 263 pic16lf1904/6/7 25.2 package details the following sections give the technical details of the packages. e1 n note 1 1 23 d a a1 b b1 e l a2 eb c e
pic16lf1904/6/7 ds41569a-page 264 preliminary ? 2011 microchip technology inc. c h h l l1 a2 a1 a note 1 12 3 b e e e1 d n
? 2011 microchip technology inc. preliminary ds41569a-page 265 pic16lf1904/6/7 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16lf1904/6/7 ds41569a-page 266 preliminary ? 2011 microchip technology inc. l l1 c a2 a1 a e e1 d n 1 2 note 1 b e
? 2011 microchip technology inc. preliminary ds41569a-page 267 pic16lf1904/6/7 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16lf1904/6/7 ds41569a-page 268 preliminary ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. preliminary ds41569a-page 269 pic16lf1904/6/7 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16lf1904/6/7 ds41569a-page 270 preliminary ? 2011 microchip technology inc. n note 1 e1 d 123 a a1 b1 be c eb e l a2
? 2011 microchip technology inc. preliminary ds41569a-page 271 pic16lf1904/6/7 a e e1 d d1 e b note 1 note 2 n 123 c a1 l a2 l1
pic16lf1904/6/7 ds41569a-page 272 preliminary ? 2011 microchip technology inc.
? 2011 microchip technology inc. preliminary ds41569a-page 273 pic16lf1904/6/7 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16lf1904/6/7 ds41569a-page 274 preliminary ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. preliminary ds41569a-page 275 pic16lf1904/6/7 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16lf1904/6/7 ds41569a-page 276 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 277 pic16lf1904/6/7 appendix a: data sheet revision history revision a original release (03/2011).
pic16lf1904/6/7 ds41569a-page 278 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 279 pic16lf1904/6/7 index a a/d specifications............................................................ 252 absolute maximum ratings .............................................. 237 ac characteristics industrial and extended ............................................ 246 load conditions ........................................................ 245 adc .................................................................................. 125 acquisition requirements ......................................... 135 associated registers.................................................. 137 block diagram........................................................... 125 calculating acquisition time..................................... 135 channel selection..................................................... 126 configuration............................................................. 126 configuring interrupt ................................................. 130 conversion clock...................................................... 126 conversion procedure .............................................. 130 internal sampling switch (r ss ) impedance.............. 135 interrupts................................................................... 128 operation .................................................................. 129 operation during sleep ............................................ 129 port configuration ..................................................... 126 reference voltage (v ref )......................................... 126 source impedance.................................................... 135 starting an a/d conversion ...................................... 128 adcon0 register....................................................... 31, 131 adcon1 register....................................................... 31, 132 addfsr ........................................................................... 227 addwfc .......................................................................... 227 adresh register............................................................... 31 adresh register (adfm = 0) ......................................... 133 adresh register (adfm = 1) ......................................... 134 adresl register ............................................................... 31 adresl register (adfm = 0).......................................... 133 adresl register (adfm = 1).......................................... 134 analog-to-digital converter. see adc ansela register ............................................................. 104 anselb register ............................................................. 107 ansele register ............................................................. 115 assembler mpasm assembler................................................... 258 b baudcon register.......................................................... 166 block diagrams adc .......................................................................... 125 adc transfer function ............................................. 136 analog input model ................................................... 136 clock source............................................................... 58 core ............................................................................ 20 crystal operation ........................................................ 60 eusart receive ..................................................... 156 eusart transmit .................................................... 155 generic i/o port ........................................................ 101 interrupt logic ............................................................. 67 lcd bias voltage generation................................... 193 lcd clock generation .............................................. 192 on-chip reset circuit ................................................. 49 pic16lf1904/6/7........................................................ 14 timer0....................................................................... 139 timer1....................................................................... 143 timer1 gate .............................................. 148, 149, 150 voltage reference .................................................... 121 borcon register.............................................................. 51 bra .................................................................................. 228 break character (12-bit) transmit and receive ............... 175 brown-out reset (bor)...................................................... 51 specifications ........................................................... 250 timing and characteristics ....................................... 248 c c compilers mplab c18.............................................................. 258 call................................................................................. 229 callw ............................................................................. 229 clock accuracy with asynchronous operation ................. 164 clock sources external modes........................................................... 59 ec ...................................................................... 59 internal modes............................................................ 60 hfintosc ......................................................... 60 internal oscillator clock switch timing .............. 61 lfintosc.......................................................... 61 clock switching .................................................................. 63 code examples a/d conversion ........................................................ 130 initializing porta .................................................... 101 writing to flash program memory.............................. 94 comparators c2out as t1 gate................................................... 145 config1 register ............................................................. 44 config2 register ............................................................. 45 core function register....................................................... 30 customer change notification service............................. 285 customer notification service .......................................... 285 customer support............................................................. 285 d data memory ...................................................................... 24 dc and ac characteristics............................................... 255 dc characteristics extended and industrial............................................ 242 industrial and extended............................................ 239 development support ....................................................... 257 device configuration .......................................................... 43 code protection.......................................................... 46 configuration word..................................................... 43 user id ................................................................. 46, 47 device id register.............................................................. 47 device overview........................................................... 13, 81 e eedatl register ............................................................... 98 electrical specifications .................................................... 237 enhanced mid-range cpu ................................................ 19 enhanced universal synchronous asynchronous receiver transmitter (eusart) .............................. 155 errata .................................................................................. 11 eusart ........................................................................... 155 asynchronous mode................................................. 157 12-bit break transmit and receive .................. 175 associated registers, receive......................... 163 associated registers, transmit........................ 159 auto-wake-up on break ................................... 173 baud rate generator (brg) ............................ 167 clock accuracy................................................. 164 receiver ........................................................... 160
pic16lf1904/6/7 ds41569a-page 280 preliminary ? 2011 microchip technology inc. setting up 9-bit mode with address detect....... 162 transmitter........................................................ 157 baud rate generator (brg) associated registers ........................................ 168 auto baud rate detect ..................................... 172 baud rate error, calculating ............................ 167 baud rates, asynchronous modes................... 169 formulas ........................................................... 167 high baud rate select (brgh bit)................... 167 clock polarity synchronous mode ........................................... 176 data polarity asynchronous receive ..................................... 160 data polarity asynchronous transmit .................................... 157 synchronous mode ........................................... 176 interrupts asynchronous receive ..................................... 161 asynchronous transmit .................................... 157 synchronous master mode ............................... 176, 181 associated registers, receive ......................... 180 associated registers, transmit ................ 177, 182 reception.......................................................... 179 transmission..................................................... 176 synchronous slave mode associated registers, receive ......................... 183 reception.......................................................... 183 transmission..................................................... 181 extended instruction set addfsr ................................................................... 227 f firmware instructions........................................................ 223 fixed voltage reference (fvr) associated registers ................................................ 122 flash program memory............................................... 85, 100 associated registers ................................................ 100 configuration word w/ flash program memory ........ 100 erasing........................................................................ 89 modifying..................................................................... 95 write verify ................................................................. 97 writing......................................................................... 91 fsr0h register .................................................................. 30 fsr0l register................................................................... 30 fsr1h register .................................................................. 30 fsr1l register................................................................... 30 fvrcon (fixed voltage reference control) register ..... 122 i indf0 register ................................................................... 30 indf1 register ................................................................... 30 indirect addressing ............................................................. 38 instruction format ............................................................. 224 instruction set ................................................................... 223 addlw ..................................................................... 227 addwf ..................................................................... 227 addwfc .................................................................. 227 andlw ..................................................................... 227 andwf ..................................................................... 227 bra........................................................................... 228 call ......................................................................... 229 callw...................................................................... 229 lslf ......................................................................... 231 lsrf ......................................................................... 231 movf........................................................................ 231 moviw ..................................................................... 232 movlb ..................................................................... 232 movwi ..................................................................... 233 option .................................................................... 233 reset...................................................................... 233 subwfb .................................................................. 235 tris ......................................................................... 236 bcf .......................................................................... 228 bsf........................................................................... 228 btfsc ...................................................................... 228 btfss ...................................................................... 228 call......................................................................... 229 clrf ........................................................................ 229 clrw ....................................................................... 229 clrwdt .................................................................. 229 comf ....................................................................... 229 decf ........................................................................ 229 decfsz ................................................................... 230 goto ....................................................................... 230 incf ......................................................................... 230 incfsz..................................................................... 230 iorlw ...................................................................... 230 iorwf...................................................................... 230 movlw .................................................................... 232 movwf .................................................................... 232 nop .......................................................................... 233 retfie ..................................................................... 234 retlw ..................................................................... 234 return................................................................... 234 rlf ........................................................................... 234 rrf .......................................................................... 235 sleep ...................................................................... 235 sublw ..................................................................... 235 subwf..................................................................... 235 swapf ..................................................................... 236 xorlw .................................................................... 236 xorwf .................................................................... 236 intcon register................................................................ 72 internal oscillator block intosc specifications ................................................... 246 internal sampling switch (r ss ) impedance...................... 135 internet address ............................................................... 285 interrupt-on-change......................................................... 117 associated registers ................................................ 119 interrupts............................................................................. 67 adc .......................................................................... 130 associated registers w/ interrupts............................... 77 configuration word w/ clock sources ........................ 65 tmr1 ........................................................................ 147 intosc specifications ..................................................... 246 iocbf register ................................................................ 118 iocbn register ................................................................ 118 iocbp register ................................................................ 118 l lata register .................................................................. 103 latb register .................................................................. 106 latc register .................................................................. 109 latd register .................................................................. 112 late register .................................................................. 115 lcd associated registers ................................................ 218 bias voltage generation................................... 193, 194 clock source selection............................................. 192 configuring the module............................................. 217 disabling the module ................................................ 217
? 2011 microchip technology inc. preliminary ds41569a-page 281 pic16lf1904/6/7 frame frequency...................................................... 200 interrupts................................................................... 213 lcdcon register .................................................... 185 lcdps register........................................................ 185 multiplex types ......................................................... 200 operation during sleep ............................................ 215 pixel control.............................................................. 200 prescaler................................................................... 192 segment enables...................................................... 200 waveform generation............................................... 202 lcdcon register .................................................... 185, 187 lcdcst register ............................................................. 190 lcddatax registers ............................................... 191, 198 lcdps register........................................................ 185, 188 lp bits....................................................................... 192 lcdref register ............................................................. 189 lcdrl register ................................................................ 198 lcdsen registers............................................................ 191 liquid crystal display (lcd) driver .................................. 185 load conditions ................................................................ 245 lslf ................................................................................. 231 lsrf ................................................................................. 231 m mclr .................................................................................. 52 internal ........................................................................ 52 memory organization data ............................................................................ 24 program ...................................................................... 21 microchip internet web site.............................................. 285 moviw ............................................................................. 232 movlb ............................................................................. 232 movwi ............................................................................. 233 mplab asm30 assembler, linker, librarian ................... 258 mplab integrated development environment software .. 257 mplab pm3 device programmer .................................... 260 mplab real ice in-circuit emulator system................. 259 mplink object linker/mplib object librarian ................ 258 o opcode field descriptions ............................................. 223 option ............................................................................ 233 option_reg register .................................................... 141 osccon register.............................................................. 64 oscillator associated registers .................................................. 65 oscillator module ................................................................ 57 ech ............................................................................ 57 ecl ............................................................................. 57 ecm ............................................................................ 57 intosc ...................................................................... 57 oscillator parameters ....................................................... 246 oscillator specifications.................................................... 246 oscillator start-up timer (ost) specifications............................................................ 250 oscstat register............................................................. 65 p package diagrams pic16lf1904/7..................................................... 6, 7, 8 pic16lf1906............................................................ 4, 5 packaging ......................................................................... 261 marking ............................................................. 261, 262 pdip details.............................................................. 263 pcl and pclath ............................................................... 20 pcl register....................................................................... 30 pclath register ............................................................... 30 pcon register ............................................................. 31, 55 pie1 register ............................................................... 31, 73 pie2 register ............................................................... 31, 74 pinout descriptions pic16lf1904/6/7 ....................................................... 15 pir1 register ............................................................... 31, 75 pir2 register ............................................................... 31, 76 pmadr registers............................................................... 85 pmadrh registers ............................................................ 85 pmadrl register .............................................................. 98 pmadrl registers............................................................. 85 pmcon1 register ........................................................ 85, 99 pmcon2 register ...................................................... 85, 100 pmdath register .............................................................. 98 porta ............................................................................. 102 ansela register ..................................................... 102 associated registers................................................ 104 configuration word w/ porta................................. 104 lata register ............................................................ 32 porta register......................................................... 31 specifications ........................................................... 247 porta register ............................................................... 103 portb ............................................................................. 105 anselb register ..................................................... 105 associated registers................................................ 107 latb register ............................................................ 32 portb register......................................................... 31 portb register ............................................................... 106 portc ............................................................................. 108 associated registers................................................ 110 latc register ............................................................ 32 portc register......................................................... 31 specifications ........................................................... 247 portc register............................................................... 109 portd ............................................................................. 111 associated registers................................................ 113 latd register ............................................................ 32 portdregister.......................................................... 31 portd register............................................................... 112 porte ............................................................................. 114 associated registers................................................ 116 late register ............................................................ 32 porte register......................................................... 31 porte register ............................................................... 114 power-down mode (sleep)................................................. 79 associated registers.................................................. 80 power-on reset .................................................................. 50 power-up time-out sequence ............................................ 52 power-up timer (pwrt) .................................................... 50 specifications ........................................................... 250 precision internal oscillator parameters .......................... 246 program memory ................................................................ 21 map and stack (bank 15) ........................................... 29 map and stack (bank 31) ........................................... 29 map and stack (banks 0-7) ........................................ 27 map and stack (banks 16-23) .................................... 28 map and stack (banks 24-30) .................................... 28 map and stack (banks 8-14) ...................................... 28 map and stack (pic16lf1904) .................................. 22 map and stack (pic16lf1906/7) ............................... 22 reading memory ........................................................ 23 programming, device instructions.................................... 223
pic16lf1904/6/7 ds41569a-page 282 preliminary ? 2011 microchip technology inc. r rcreg ............................................................................. 162 rcreg register................................................................. 32 rcsta register.......................................................... 32, 165 reader response ............................................................. 286 read-modify-write operations.......................................... 223 register rcreg register....................................................... 172 registers adcon0 (adc control 0) ........................................ 131 adcon1 (adc control 1) ........................................ 132 adresh (adc result high) with adfm = 0)........... 133 adresh (adc result high) with adfm = 1)........... 134 adresl (adc result low) with adfm = 0) ............ 133 adresl (adc result low) with adfm = 1) ............ 134 ansela (porta analog select)............................. 104 anselb (portb analog select)............................. 107 ansele (porte analog select)............................. 115 baudcon (baud rate control) ............................... 166 borcon brown-out reset control)........................... 51 configuration word 1 .................................................. 44 configuration word 2 .................................................. 45 core function, summary ............................................ 30 device id .................................................................... 47 eedatl (eeprom data) .......................................... 98 fvrcon................................................................... 122 intcon (interrupt control) ......................................... 72 iocbf (interrupt-on-change flag) ........................... 118 iocbn (interrupt-on-change negative edge) .......... 118 iocbp (interrupt-on-change positive edge) ............ 118 lata (data latch porta) ....................................... 103 latb (data latch portb) ....................................... 106 latc (data latch portc) ...................................... 109 latd (data latch portd) ...................................... 112 late (data latch porte) ....................................... 115 lcdcon (lcd control)............................................ 187 lcdcst (lcd contrast control) .............................. 190 lcddatax (lcd data) .................................... 191, 198 lcdps (lcd phase) ................................................ 188 lcdref (lcd reference voltage control).............. 189 lcdrl (lcd reference voltage control) ................ 198 lcdsen (lcd segment enable) .............................. 191 option_reg (option) ......................................... 141 osccon (oscillator control) ..................................... 64 oscstat (oscillator status) ..................................... 65 pcon (power control register) ................................. 55 pcon (power control) ............................................... 55 pie1 (peripheral interrupt enable 1) ........................... 73 pie2 (peripheral interrupt enable 2) ........................... 74 pir1 (peripheral interrupt register 1) ........................ 75 pir2 (peripheral interrupt request 2) ........................ 76 pmadrl (program memory address)........................ 98 pmcon1 (program memory control 1) ...................... 99 pmcon2 (program memory control 2) .................... 100 pmdath (program memory data) ............................. 98 porta...................................................................... 103 portb...................................................................... 106 portc ..................................................................... 109 portd ..................................................................... 112 porte...................................................................... 114 rcsta (receive status and control)....................... 165 special function, summary ........................................ 31 status ...................................................................... 25 t1con (timer1 control)........................................... 151 t1gcon (timer1 gate control) ............................... 152 trisa (tri-state porta)......................................... 103 trisb (tri-state portb)......................................... 106 trisc (tri-state portc) ........................................ 109 trisd (tri-state portd) ........................................ 112 trise (tri-state porte)......................................... 114 txsta (transmit status and control) ...................... 164 wdtcon (watchdog timer control) ......................... 83 wpub (weak pull-up portb)................................. 107 reset.............................................................................. 233 reset instruction................................................................. 52 resets................................................................................. 49 associated registers .................................................. 56 revision history................................................................ 277 s software simulator (mplab sim) .................................... 259 spbrg ............................................................................. 167 spbrg register................................................................. 32 spbrgh........................................................................... 167 special function registers (sfrs)..................................... 31 stack................................................................................... 36 accessing ................................................................... 36 reset .......................................................................... 38 stack overflow/underflow .................................................. 52 status register ............................................................... 25 subwfb .......................................................................... 235 t t1con register ......................................................... 31, 151 t1gcon register ............................................................ 152 temperature indicator module.......................................... 123 thermal considerations.................................................... 244 timer0............................................................................... 139 associated registers ................................................ 141 operation .................................................................. 139 specifications ........................................................... 251 timer1............................................................................... 143 associated registers ................................................. 153 asynchronous counter mode ................................... 145 reading and writing ......................................... 145 clock source selection............................................. 144 interrupt .................................................................... 147 operation .................................................................. 144 operation during sleep ............................................ 147 oscillator................................................................... 145 prescaler .................................................................. 145 specifications ........................................................... 251 timer1 gate selecting source .............................................. 145 tmr1h register ....................................................... 143 tmr1l register........................................................ 143 timers timer1 t1con ............................................................. 151 t1gcon........................................................... 152 timing diagrams a/d conversion......................................................... 253 a/d conversion (sleep mode) .................................. 253 asynchronous reception.......................................... 163 asynchronous transmission..................................... 158 asynchronous transmission (back to back) ............ 159 auto wake-up bit (wue) during normal operation . 174 auto wake-up bit (wue) during sleep .................... 174 automatic baud rate calculator............................... 173 brown-out reset (bor)............................................ 248 brown-out reset situations ........................................ 51
? 2011 microchip technology inc. preliminary ds41569a-page 283 pic16lf1904/6/7 clkout and i/o....................................................... 247 int pin interrupt.......................................................... 70 internal oscillator switch timing................................. 62 lcd interrupt timing in quarter-duty cycle drive.... 214 lcd sleep entry/exit when slpen = 1 or cs = 00 . 216 reset start-up sequence............................................ 53 reset, wdt, ost and power-up timer ................... 248 send break character sequence ............................. 175 spi slave mode (cke = 0) ....................................... 254 synchronous reception (master mode, sren) ....... 180 synchronous transmission....................................... 177 synchronous transmission (through txen) ........... 177 timer0 and timer1 external clock ........................... 250 timer1 incrementing edge........................................ 147 type-a in 1/2 mux, 1/2 bias drive ........................... 203 type-a in 1/2 mux, 1/3 bias drive ........................... 205 type-a in 1/3 mux, 1/2 bias drive ........................... 207 type-a in 1/3 mux, 1/3 bias drive ........................... 209 type-a in 1/4 mux, 1/3 bias drive ........................... 211 type-a/type-b in static drive................................... 202 type-b in 1/2 mux, 1/2 bias drive ........................... 204 type-b in 1/2 mux, 1/3 bias drive ........................... 206 type-b in 1/3 mux, 1/2 bias drive ........................... 208 type-b in 1/3 mux, 1/3 bias drive ........................... 210 type-b in 1/4 mux, 1/3 bias drive ........................... 212 wake-up from interrupt ............................................... 80 timing parameter symbology........................................... 245 tmr0 register.................................................................... 31 tmr1h register ................................................................. 31 tmr1l register.................................................................. 31 tris.................................................................................. 236 trisa register ........................................................... 31, 103 trisb ............................................................................... 105 trisb register ........................................................... 31, 106 trisc ............................................................................... 108 trisc register........................................................... 31, 109 trisd ............................................................................... 111 trisd register........................................................... 31, 112 trise ............................................................................... 114 trise register ........................................................... 31, 114 txreg.............................................................................. 157 txreg register ................................................................. 32 txsta register .......................................................... 32, 164 brgh bit .................................................................. 167 u usart synchronous master mode requirements, synchronous transmission ...... 254 v v ref . s ee adc reference voltage w wake-up on break ............................................................ 173 wake-up using interrupts ................................................... 80 watchdog timer (wdt) ...................................................... 52 modes ......................................................................... 82 specifications............................................................ 250 wdtcon register ............................................................. 83 wpub register................................................................. 107 write protection .................................................................. 46 www address.................................................................. 285 www, on-line support ..................................................... 11
pic16lf1904/6/7 ds41569a-page 284 preliminary ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. preliminary ds41569a-page 285 pic16lf1904/6/7 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
pic16lf1904/6/7 ds41569a-page 286 preliminary ? 2011 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41569a pic16lf1904/6/7 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2011 microchip technology inc. preliminary ds41569a-page 287 pic16lf1904/6/7 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16lf1904, pic16lf1906, pic16lf1907 tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: i= -40 ? c to +85 ? c(industrial) e= -40 ? c to +125 ? c (extended) package: mv = uqfn p=pdip pt = tqfp 44 p so = soic ss = ssop pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16lf1904t - i/mv 301 tape and reel, industrial temperature, uqfn package, qtp pattern #301 b) pic16lf1906 - i/p industrial temperature pdip package c) pic16lf1906 - e/ss extended temperature, ssop package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. [x] (1) tape and reel option -
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